NAND Flash Memory Dummy Cell Voltage Control
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Solution Overview
Problem
NAND flash memory devices face issues with program inhibit cells being unintentionally programmed due to leakage currents and capacitive boosting effects, which affect the scaling down of cell size and degrade programming and erasing characteristics.
Innovation Solution
A control circuit is implemented to manage word line voltages during program and erase operations, ensuring the dummy memory cell is not programmed or erased simultaneously with other cells, and applying specific voltages to maintain channel voltage and prevent leakage, thereby reducing hot electron injection and channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy memory cells are connected in series with memory cells to maintain channel voltage during program operations, then program inhibit characteristics are improved, but device complexity increases due to additional control circuitry and voltage management requirements
Solution Approach 1:
The patent applies different word line voltages to different parts of the cell string: high voltage (e.g., 18V) to selected memory cells for programming, low voltage (e.g., 0V or 3V) to dummy memory cells to prevent programming. This local differentiation of electrical conditions enables the dummy cells to act as voltage barriers without requiring physical separation or complex additional structures.
Solution Approach 2:
The control circuit dynamically adjusts word line voltages based on the operational mode. During program operations, the control circuit applies high voltage to selected cells and low voltage to dummy cells. During read or erase operations, the voltage distribution is adjusted accordingly. This dynamic voltage control enables the same physical structure to serve multiple functions with different reliability requirements.
2Productivity
If word line voltages are applied to maintain channel voltage and prevent leakage currents, then programming efficiency is improved, but energy consumption increases due to multiple voltage applications
Solution Approach 1:
Instead of applying high programming voltage to all word lines simultaneously, the control circuit applies high voltage only to selected word lines corresponding to memory cells that need programming. Dummy memory cells receive low voltage to prevent leakage. This partial application of high voltage reduces total energy consumption while maintaining programming efficiency for the target cells.
Solution Approach 2:
The control circuit changes the voltage parameter of word lines based on operational requirements. During program operations, selected word lines receive high voltage (e.g., 18V) to enable tunneling, while dummy word lines receive low voltage (e.g., 0V or 3V) to prevent hot electron injection. This parameter differentiation achieves efficient programming with reduced overall energy consumption.
3Length of moving object
If dummy memory cells are used to prevent hot electron injection and maintain channel voltage, then cell size scalability is improved, but manufacturing precision requirements increase due to additional voltage control
Solution Approach 1:
The cell string is segmented into functional regions: memory cells that receive high voltage for programming and dummy memory cells that receive low voltage to act as voltage barriers. This segmentation allows the dummy cells to be integrated into the same physical structure as memory cells, maintaining scalability while providing precise voltage control through differential word line biasing.
Solution Approach 2:
Dummy memory cells serve as intermediary elements between the high voltage applied to selected memory cells and the ground reference. These dummy cells receive low voltage and act as voltage barriers that prevent hot electrons from injecting into the channel of non-selected cells. This intermediary approach enables cell size scalability while requiring precise voltage control through the control circuit.
4Reliability
If multiple word line voltages are applied during program operations to prevent leakage, then programming accuracy is improved, but operation complexity increases due to coordinated voltage control
Solution Approach 1:
The control circuit implements periodic or sequential voltage application: first applying high voltage to selected word lines and low voltage to dummy word lines during program operations, then adjusting voltages for read or erase operations. This periodic voltage pattern ensures programming accuracy by preventing leakage during programming while maintaining ease of operation through systematic voltage sequencing.
Solution Approach 2:
The control circuit monitors operational status and adjusts word line voltages accordingly. During program operations, the control circuit verifies that selected cells receive high voltage and dummy cells receive low voltage, ensuring programming accuracy. This feedback mechanism manages the complexity of coordinated voltage control by automatically adjusting voltages based on operational requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances program inhibit characteristics, reduces leakage currents, and prevents over-erasing of dummy memory cells, thereby improving the overall programming and erasing efficiency and maintaining cell size scalability.
Implementation Method 1
program inhibit cells being unintentionally programmed due to leakage currents and capacitive boosting effects
Implementation Method 2
reduces hot electron injection and channel length
Data Source
AI summary
A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.