NAND Flash Dummy Cells Reduce GIDL Write Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In NAND-type flash memory, miniaturization leads to increased erroneous writes due to gate-induced drain leakage (GIDL) current, especially in non-selected cells adjacent to select gate transistors, which conventional channel voltage control schemes fail to adequately address.
Innovation Solution
Incorporating dummy cells adjacent to select gate transistors with a threshold voltage higher than the erase state of memory cells, and employing specific erase and programming algorithms to set these dummy cells in a state that reduces the write error rate by isolating and boosting their channels independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If miniaturization of NAND-type flash memory is enhanced, then unit cell area is reduced and capacity is increased, but write error rate increases due to GIDL current in non-selected cells adjacent to select gate transistors
Solution Approach 1:
A dummy cell is introduced as an intermediary element between the select gate transistor and the actual memory cells. This dummy cell serves as a buffer that prevents GIDL current from directly affecting the data storage cells, thereby reducing write errors while maintaining miniaturization benefits
Solution Approach 2:
The harmful function of the cell adjacent to the select gate transistor is extracted and transferred to a dedicated dummy cell. The dummy cell absorbs the GIDL current effects that would otherwise cause erroneous writes in functional memory cells, isolating the problem from the data storage function
2Productivity
If conventional channel voltage control schemes are used, then data programming is performed, but erroneous writes occur in non-selected cells adjacent to select gate transistors
Solution Approach 1:
The NAND cell unit is segmented into functional memory cells and a separate dummy cell region. This segmentation allows independent control and protection mechanisms to be applied to each region, enabling data programming while preventing erroneous writes in the dummy cell area from propagating to functional cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly reduces the write error rate by preventing erroneous writes in non-selected cells, even in highly miniaturized NAND-type flash memory designs, by effectively managing the channel voltage and threshold states of dummy cells.
Implementation Method 1
dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell
Implementation Method 2
data write is performed to inject electrons into the floating gate from the cell channel by FN tunneling with applying write voltage Vpgm to a selected word line
Implementation Method 3
the selected cell's channel is boosted by capacitive coupling from a selected word line, and electron injection into the floating gate will be inhibited
Implementation Method 4
a large electric field is applied between the floating gate and the channel in the selected cell, so that electrons are injected into the floating gate
Data Source
AI summary
A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.