NAND Flash Erase Sequence for E0 Loss and Read Margin Control

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Solution Overview

Problem

Existing NAND Flash memory devices face issues with threshold voltage shifts (E0 loss) due to shallow holes accumulating in the charge trap layer during erase operations, affecting the read window margin at the erased state.

Innovation Solution

A pre-erase scheme is introduced where memory cells are pre-erased with a supply voltage not exceeding 1 volt, followed by immediate programming and subsequent regular erase without intermediate verification, to reduce shallow holes and maintain threshold voltage distributions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a regular erase operation is performed on NAND Flash memory cells, then the memory cells are erased to the E0 state, but shallow holes accumulate in the charge trap layer causing threshold voltage shifts (E0 loss) and reduced read window margin

Engineering Contradiction:

Improveread window marginVSAvoidshallow holes accumulation

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies a preliminary action by performing a pre-erase operation before the main erase operation. This pre-erase step prepares the memory cells by partially erasing them first, which prevents shallow holes from accumulating during the subsequent main erase operation, thereby maintaining threshold voltage stability and read window margin.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The pre-erase operation serves as a preliminary anti-action that counteracts the harmful effect of shallow holes accumulation before it occurs. By applying a controlled erase voltage in advance, the patent creates conditions that prevent the formation of shallow holes during the main erase operation, thus protecting against E0 loss.

Inventive Principle:

Principle #9Preliminary anti-action

2Productivity

If pre-erase, program, and erase operations are performed sequentially without intermediate verification, then erase operation efficiency is improved, but the complexity of the erase sequence increases

Engineering Contradiction:

Improveerase operation efficiencyVSAvoiderase sequence complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple operations (pre-erase, program, and main erase) into a single integrated erase sequence. By combining these operations and eliminating intermediate verification steps, the patent improves erase operation efficiency while managing complexity through a streamlined unified process.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent maintains continuity of useful action by performing pre-erase, program, and main erase operations in an uninterrupted sequential manner without intermediate verification pauses. This continuous operation maximizes productivity by keeping the memory device actively engaged in useful operations throughout the entire erase sequence.

Inventive Principle:

Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The pre-erase scheme significantly reduces E0 loss and maintains the read window margin by allowing shallow holes to escape or transition to higher energy levels, improving the erase operation efficiency.

Implementation Method 1

allowing shallow holes to escape or transition to higher energy levels

Methodology Applied

Scientific EffectCharge trap layer energy level transition:

Implementation Method 2

program the block of memory cells after pre-erasing the block of memory cells

Methodology Applied

Scientific EffectCharge injection:

Implementation Method 3

erase the block of memory cells after programming the block of memory cells

Methodology Applied

Scientific EffectCharge removal:

Data Source

PatentUS20260017187A1Memory device and operation thereof

Publication Date: 2026.01.15 YANGTZE MEMORY TECH CO LTD

AI summary

In certain aspects, a memory device includes a block of memory cells, and a peripheral circuit coupled to the block of memory cells. The peripheral circuit is configured to, in an erase operation, pre-erase the block of memory cells, program the block of memory cells after pre-erasing the block of memory cells, and erase the block of memory cells after programming the block of memory cells.