NAND Flash Memory Erase Operation Bias Control
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Solution Overview
Problem
Conventional NAND Flash memory devices require additional time to complete an erase operation due to uneven bias conditions affecting memory cells, leading to inefficiencies in erase operations.
Innovation Solution
Implementing a method that adjusts bias conditions during an erase operation by using 'dummy' word lines and controlling string driver transistors to reduce the potential difference between active and adjacent word lines, allowing for a more uniform erase process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional erase operations are performed without adjusting bias conditions, then the erase operation can be performed with simple control, but the erase operation time is extended due to uneven bias conditions
Solution Approach 1:
The patent applies preliminary action by adjusting the bias conditions of word lines and select gates before the erase operation begins. Specifically, dummy word lines are biased to match the potential of adjacent active word lines, and select gates are biased to reduce electric field disparities. This preliminary bias adjustment ensures uniform erase conditions across all memory cells, preventing the time extension that would otherwise occur due to uneven erasure rates.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the voltage potentials of various word lines and select gates during the erase operation. The method involves changing the bias parameters of dummy word lines to match adjacent active word lines, and adjusting select gate biases to minimize electric field differences. These parameter adjustments create uniform erase conditions throughout the memory array, resolving the time loss issue without requiring complex additional hardware.
2Manufacturing precision
If dummy word lines are used to adjust bias conditions, then erase uniformity is improved, but the device structure becomes more complex
Solution Approach 1:
The patent applies universality by making existing dummy word lines serve multiple functions: they act as both structural placeholders during fabrication and as active bias control elements during erase operations. The same dummy word line structures that are already present in the memory array are repurposed to provide the necessary bias adjustment, eliminating the need for additional dedicated structures and avoiding increased device complexity while achieving improved erase uniformity.
Solution Approach 2:
The patent implements self-service by using the existing dummy word line structures within the memory array to provide their own bias control function. Rather than requiring external control mechanisms or additional dedicated structures, the dummy word lines themselves are biased to match adjacent active word lines, creating a self-regulating system that improves erase uniformity without adding external complexity to the device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time required for erase operations and improves the efficiency of memory cell erasure by minimizing the electric field disparities, thereby enhancing overall memory device performance.
Implementation Method 1
applying a ramped increasing bias potential to a p-well of a string of memory cells
Data Source
AI summary
Erase operations and apparatus configured to perform the erase operations are suitable for non-volatile memory devices having memory cells arranged in strings. One such method includes biasing select gate control lines of a string of memory cells to a first bias potential, biasing access lines of a pair of the memory cells to a second bias potential and biasing access lines of one or more remaining memory cells to a third potential. A ramping bias potential is applied to channel regions of the string of memory cells substantially concurrently with or subsequent to biasing the select gate control lines and the access lines, and floating the select gate control lines in response to the ramping bias potential reaching a release bias potential between an initial bias potential of the ramping bias potential and a target bias potential of the ramping bias potential.