NAND Flash Memory Erase Voltage Control via Well Detection
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Solution Overview
Problem
NAND flash memory erase operations are hindered by off-leakage currents in selection transistors, leading to inefficient erase voltage rise and increased power consumption due to the sharing of a P well among blocks, causing erase disturbances and prolonged erasing times.
Innovation Solution
A method that detects the voltage of the well region during an erase pulse and adjusts the voltage applied to the selection transistors based on the detected voltage to control the off-leakage current, optimizing the global word line voltage to enhance erase speed and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the global word line voltage is increased to reduce off-leakage current, then power consumption is reduced, but the erase speed becomes slow
Solution Approach 1:
The patent applies dynamic voltage adjustment to the global word line, switching between different voltage levels (0V, 0.5V, 1.0V) based on the erase operation phase. During voltage rise phase, higher voltage (1.0V) is applied to suppress off-leakage current, while during stable erase phase, lower voltage (0V or 0.5V) is used to maintain erase speed, thus dynamically optimizing the trade-off between power consumption and erase speed
Solution Approach 2:
The patent changes the voltage parameter of the global word line dynamically during the erase operation. By adjusting the voltage level according to the operational phase (voltage rise phase vs. stable erase phase), the system optimizes both power consumption and erase speed by matching the voltage parameter to the specific operational requirements at each phase
2Productivity
If the erase voltage is applied to the P well, then the erase operation is performed, but the off-leakage current causes the capacitance to increase and slows down the voltage rise
Solution Approach 1:
The patent applies preliminary action by pre-charging or pre-biasing the global word line to an intermediate voltage level (0.5V or 1.0V) before initiating the erase operation. This preliminary voltage application reduces the off-leakage current in advance, thereby reducing the effective capacitance that needs to be charged during the erase operation and accelerating the voltage rise to the P well
Solution Approach 2:
The patent applies preliminary anti-action by applying a counter-voltage or counter-current to the global word line before the erase operation begins. This preliminary counter-action suppresses the off-leakage current that would otherwise slow down the voltage rise, effectively counteracting the harmful capacitive effect before it can significantly impact the erase timing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for rapid increase of the erase voltage while minimizing off-leakage currents, thereby shortening erasing time and reducing power consumption in NAND flash memory devices.
Implementation Method 1
a detection member for detecting a voltage of the well region after the erase pulse is applied
Implementation Method 2
a control member for controlling the third voltage based on the voltage detected by the detection member
Data Source
AI summary
The present invention provides a semiconductor memory device capable of performing rapid erasing while reducing power consumption. In the flash memory of the present invention, the voltage of the P well is detected by the voltage detecting unit 200 during the erasing operation. When the voltage is lower than the threshold value, it is determined that the off leakage current of the selection transistor of the non-selection block is large, and the voltage of the global word line at the time of applying the next erase pulse is increased. When the voltage is above the threshold value, it is determined that the off leakage current is small, and the voltage of the global word line at the time of applying the next erase pulse is maintained.