NAND Flash Facing Bar for Channel Extension and Area Reduction
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Solution Overview
Problem
Conventional NAND flash memory devices face issues such as short channel effects, leakage currents, gate induced drain leakage, drain induced barrier lowering, program disturbances, and increased trap charge loss due to reduced channel lengths and interference between adjacent transistors, leading to variations in threshold voltage.
Innovation Solution
A NAND flash memory device with a facing bar protruding from a semiconductor substrate, divided into active regions, featuring side structures with conductive base electrode guards and trap guards, allowing for extended transmission channels and minimized layout area, fabricated through processes including isolation trench formation, facing bar creation, material stacking, gate deposition, and air gap formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel length of cell transistor is reduced to improve integration density, then productivity is improved, but reliability deteriorates due to short channel effects and leakage currents
Solution Approach 1:
The patent transitions from planar transistor configuration to vertically stacked three-dimensional transistor structure. Multiple cell transistors are stacked along the vertical direction (third direction) on the semiconductor substrate, allowing integration density improvement without reducing channel length in the lateral plane, thereby maintaining transistor reliability while achieving higher productivity
Solution Approach 2:
The semiconductor substrate is divided into multiple stacked layers with isolation trenches between them. Each layer contains cell transistors that are electrically isolated from other layers, allowing independent operation and maintaining reliable transistor performance while enabling high-density vertical integration
2Area of stationary object
If channel length is reduced to increase integration, then area is reduced, but harmful factors increase due to gate induced drain leakage and drain induced barrier lowering
Solution Approach 1:
The invention utilizes vertical stacking to reduce lateral layout area while maintaining sufficient channel length in the vertical direction. The channel extends through the thickness of each transistor layer, providing adequate channel length to minimize GIDL and DIBL effects while achieving compact area footprint
Solution Approach 2:
Different regions of the stacked structure are optimized for different functions: control gates are positioned to provide localized electric field control, trap gates are placed to capture charges in specific regions, and isolation trenches are inserted between layers to locally suppress leakage currents, thereby reducing harmful effects while maintaining compact area
3Ease of manufacture
If transistors are arranged in planar configuration to simplify fabrication, then ease of manufacture is improved, but reliability deteriorates due to interference between adjacent transistors
Solution Approach 1:
The semiconductor substrate is segmented into multiple isolated layers by insertion trenches filled with insulating material. This segmentation electrically isolates transistors in different layers, preventing interference between adjacent transistors while maintaining stable threshold voltage. The segmented structure can still be fabricated using standard semiconductor processing techniques
Solution Approach 2:
Isolation trenches filled with insulating material act as intermediary elements between stacked transistor layers. These intermediary structures provide electrical isolation and prevent charge interference between adjacent layers, ensuring threshold voltage stability while allowing the use of conventional fabrication processes
Data Source
AI summary
A NAND flash memory device having a facing bar and a method of fabricating the same are provided. The method includes forming one transistor or a plurality of stack transistors as cell transistors on two side surfaces of a facing bar to have transmission channels thereat. In this case, the height of the facing bar may be easily increased. Thus, not only a layout area of unit transistors including the cell transistors but also a layout area of cell strings may be minimized, and lengths of the transmission channels of the cell transistors may be sufficiently extended. As a result, according to the NAND flash memory device and the method of fabricating the same, the overall operating characteristics are improved.