NAND Flash Memory Interconnect Resistance Reduction
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Solution Overview
Problem
High interconnect resistance in cell source lines and cell well lines of NAND-type nonvolatile semiconductor memory devices hinders efficient data reading and increases charge/discharge time, leading to reduced performance and integration capacity.
Innovation Solution
The implementation of a second interconnect layer with lower sheet resistance for cell well lines and a second cell source line arranged in a mesh configuration, connected to source terminals of select transistors, reduces interconnect resistance and enhances data reading efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single interconnect layer is used for cell source lines and cell well lines, then device structure is simple, but interconnect resistance is high leading to increased RC time constant and reduced performance
Solution Approach 1:
The patent transitions from a single-planar interconnect layer to a three-dimensional multi-layer interconnect structure. Cell well lines are routed in a first interconnect layer while cell source lines are routed in a second interconnect layer, vertically stacked above the first layer. This dimensional transition reduces in-plane routing congestion and allows independent optimization of each line type, thereby reducing interconnect resistance and RC time constant without compromising device structure simplicity.
Solution Approach 2:
The patent segments the interconnect system into multiple independent layers, with each layer dedicated to specific signal types (cell well lines in the first layer, cell source lines in the second layer). This segmentation allows each layer to be optimized independently for its specific function, reducing overall interconnect resistance and improving performance while maintaining manageable structural complexity.
2Ease of manufacture
If cell source lines and cell well lines are routed in the same interconnect layer, then manufacturing process is simple, but interconnect resistance increases and charge/discharge time increases
Solution Approach 1:
The patent resolves the manufacturing complexity by adding a vertical dimension to the interconnect structure. Cell well lines and cell source lines are routed in separate layers (first and second interconnect layers respectively), connected through vertical vias. This approach maintains relatively simple planar routing within each layer while achieving reduced interconnect resistance and faster charge/discharge times through the three-dimensional configuration.
3Reliability
If shunt regions are enlarged to accommodate cell source lines and cell well lines, then interconnect resistance is reduced, but memory array area increases reducing integration density
Solution Approach 1:
The patent eliminates the need for enlarged shunt regions by transitioning to a multi-layer interconnect structure. Cell source lines and cell well lines are routed in separate vertical layers, allowing them to pass through or adjacent to memory cell regions without requiring large lateral shunt regions. This vertical routing approach reduces the lateral footprint and improves integration density while maintaining low interconnect resistance.
Solution Approach 2:
The patent segments the interconnect paths into multiple layers, allowing cell source lines and cell well lines to be routed independently through different vertical levels. This segmentation enables the interconnect lines to bypass the need for large shunt regions by utilizing the vertical dimension, thereby reducing the memory array area while maintaining low interconnect resistance.
4Area of stationary object
If cell source driver and cell well driver sizes are reduced to improve integration, then device area is reduced, but interconnect resistance increases and performance decreases
Solution Approach 1:
The patent compensates for reduced driver sizes by implementing a multi-layer interconnect structure that reduces the overall interconnect resistance. With cell source lines and cell well lines routed in separate vertical layers, the interconnect path resistance is reduced, allowing smaller drivers to maintain adequate performance. The three-dimensional routing provides lower resistance paths that compensate for the reduced driver drive strength.
Solution Approach 2:
The patent segments the interconnect system into multiple low-resistance layers, allowing each driver to control its dedicated layer of interconnect lines. This segmentation reduces the total resistance burden on each driver, enabling smaller driver sizes while maintaining performance. Each driver operates on optimized single-layer interconnects rather than sharing high-resistance multi-layer paths.
Data Source
AI summary
A nonvolatile semiconductor memory includes a memory cell array including horizontally aligned memory cell columns, each including vertically arranged memory cell transistors and select transistors selecting the memory cell transistors; first cell well lines connecting well regions in which the memory cell columns are formed; second cell well lines arranged in an interconnect layer above the first cell well lines and connecting the first cell well lines to one another electrically; and a cell source line connecting source terminals of the select transistors in each memory cell column.