3D NAND Flash ISPP Pre-Pulse Removal for Write Time Reduction
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Solution Overview
Problem
Conventional programming methods for 3D NAND flash memory increase write time and power consumption due to interference from unselect strings during the program verify phases, particularly when the verification voltage is lower than the threshold voltage, leading to unnecessary pre-pulse phases.
Innovation Solution
A programming method that programs a select wordline of an unselect bit line in a 3D NAND flash, performs a first verification process, and removes the pre-pulse phase of the ISPP if the verification voltage is higher than a default voltage, thereby reducing electron injection and interference between wordline layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pre-pulse phase is added before the verify phase to prevent electron injection interference, then interference from unselect strings is reduced, but write time is increased
Solution Approach 1:
The patent dynamically adjusts the verification process by detecting whether electron injection interference actually occurs during programming. When interference is detected, the pre-pulse phase is applied; when no interference is detected, the pre-pulse phase is skipped. This dynamic adaptation resolves the contradiction by making the verification process reliable only when necessary, thereby reducing overall write time while maintaining verification accuracy when needed.
Solution Approach 2:
The patent changes the verification voltage parameter during the programming process. By adjusting the verification voltage to be higher than the threshold voltage of the select memory cell, the patent prevents electron injection interference without requiring the pre-pulse phase. This parameter change resolves the contradiction by eliminating the need for the time-consuming pre-pulse phase while maintaining verification reliability through voltage adjustment.
2Reliability
If the verification voltage is kept low to avoid electron injection, then interference is reduced, but programming efficiency decreases
Solution Approach 1:
The patent dynamically adjusts the verification voltage based on the programming state. Initially, a lower verification voltage is used to avoid electron injection interference. As programming progresses and the threshold voltage increases, the verification voltage is raised to maintain programming efficiency. This dynamic voltage adjustment resolves the contradiction by optimizing electron injection control at each programming stage while maintaining overall programming efficiency.
Solution Approach 2:
The patent performs preliminary detection of electron injection interference during the programming process. By detecting whether interference occurs early in the programming sequence, the patent can determine subsequent verification voltage levels and whether to apply the pre-pulse phase. This preliminary action resolves the contradiction by enabling adaptive voltage control that prevents electron injection when needed while maintaining programming efficiency when not needed.
Data Source
AI summary
A programming method of an increment step pulse program (ISPP) for a three-dimension (3D) NAND flash includes programming a select wordline of an unselect bit line of the 3D NAND flash; performing a first verification process with at least a verification voltage on the select wordline; determining whether a first verification voltage of the first verification process for the select wordline is higher than a default voltage or not; and removing a pre-pulse phase of the ISPP when the first verification voltage is higher than the default voltage; wherein the first verification voltage is a following verification voltage of the first verification process.