NAND Flash Memory Cell Programming Reducing Floating Gate Interference
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Solution Overview
Problem
As NAND flash memory scales, parasitic capacitance coupling between adjacent memory cell floating gates increases, leading to floating gate-to-floating gate interference, which causes wider threshold voltage distributions and degrades programming performance, especially in multi-level cell (MLC) devices where the difference between adjacent threshold voltage distributions is small.
Innovation Solution
A method is introduced where the upper pages of memory cells coupled to the same select line are programmed at different times, with lower pages being programmed in parallel, and upper pages being programmed separately, using a two-pass programming process to reduce floating gate-to-floating gate interference by varying the number of storable bits across even and odd sense lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled down to increase density, then memory density is improved, but floating gate-to-floating gate interference increases
Solution Approach 1:
The patent segments the programming operation into two distinct passes: a first pass that programs even-numbered sense lines, and a second pass that programs odd-numbered sense lines. This temporal segmentation prevents simultaneous programming of adjacent cells, thereby reducing parasitic capacitance coupling and floating gate interference while maintaining high memory density through continued scaling.
2Manufacturing precision
If two-pass programming is used to reduce interference, then programming accuracy is improved, but programming time increases
Solution Approach 1:
The patent performs preliminary programming of even-numbered sense lines in the first pass, establishing a foundation that reduces interference for subsequent odd-numbered sense line programming. This preliminary action enables the second pass to achieve better programming accuracy with reduced interference, while the overall two-pass structure optimizes the balance between precision and time by preventing re-programming operations.
3Productivity
If adjacent cells are programmed simultaneously to increase productivity, then programming speed is improved, but threshold voltage distribution widens
Solution Approach 1:
The patent divides the memory array into two separate programming groups based on sense line parity (even and odd). By programming these groups sequentially in different passes rather than simultaneously, the method maintains high productivity through efficient parallel programming within each pass while preventing threshold voltage distribution widening that would result from simultaneous adjacent cell programming.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces floating gate-to-floating gate interference, maintaining accurate programming and read operations by compensating for interference effects through varying bit assignments and using a two-pass programming method, thereby improving the reliability of multi-level cell NAND flash memory devices.
Implementation Method 1
parasitic capacitance coupling between adjacent memory cell floating gates becomes a problem
Data Source
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AI summary
One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states. Such embodiments include programming, separately, the first cell to one of a third number of states based, at least in part, on the one of the first number of states and the second cell to one of a fourth number of states based, at least in part, on the one of the second number of states.