NAND Flash Memory Page Buffer Architecture
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Solution Overview
Problem
The limitations of traditional NAND flash memory architectures, where the number of page buffers is restricted due to their large circuit size, leading to limited read/write performance, as each page buffer can only connect to a single bit line, thereby restricting the number of bit lines that can be programmed or read simultaneously.
Innovation Solution
The introduction of bit line select gates that allow a page buffer to connect to multiple bit lines, enabling multiple-page programming and reading, along with additional pass gates and data registers to enhance operation, allowing simultaneous programming and reading of multiple memory cells across multiple bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of page buffers is increased to enhance read/write throughput, then memory performance is improved, but the die size occupied by page buffers increases significantly
Solution Approach 1:
The bit line select gate enables a single page buffer to serve multiple bit lines (e.g., one page buffer serving 8 bit lines), making the page buffer multi-functional. This allows the same page buffer circuit to be reused across multiple bit lines through time-multiplexed selection, thereby increasing throughput without proportionally increasing the number of page buffers and their associated die area
Solution Approach 2:
The system dynamically switches the connection between page buffers and bit lines using bit line select gates. Instead of a static one-to-one mapping, the connection is dynamically reconfigured in time slots, allowing flexible allocation of page buffer resources to multiple bit lines and maximizing throughput while minimizing the number of page buffers required
2Device complexity
If each page buffer connects to a single bit line to simplify the architecture, then device complexity is reduced, but the number of bit lines that can be programmed or read simultaneously is limited
Solution Approach 1:
The bit line select gate acts as an intermediary component between the page buffer and multiple bit lines. This intermediary enables a single page buffer to interface with multiple bit lines by selectively connecting to different bit lines at different time slots, thereby increasing simultaneous program/read capacity while maintaining relatively simple page buffer architecture
Solution Approach 2:
The system transitions from a one-dimensional (single bit line per page buffer) to a multi-dimensional connection scheme where one page buffer can access multiple bit lines through the bit line select gate. This adds a temporal dimension to the connection, allowing the same physical connection to serve multiple bit lines at different time slots
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases data read/write throughput without increasing the number of page buffers, reducing the die size and enhancing memory performance by allowing multiple bit lines to be programmed and read simultaneously.
Implementation Method 1
After each bit line is loaded with selected data, an associated bit line select gate is disabled so that the selected data is maintained on the bit line using bit line capacitance
Data Source
AI summary
Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a NAND flash memory includes setting programming conditions on word lines to set up programming of multiple memory cells associated with multiple bit lines, and sequentially enabling bit line select gates to load data from a page buffer to the multiple bit lines of the memory. After each bit line is loaded with selected data, an associated bit line select gate is disabled so that the selected data is maintained on the bit line using bit line capacitance. The method also includes waiting for a programming interval to complete after all the bit lines are loaded with data to program the multiple memory cells associated with the multiple bit lines. At least a portion of the multiple memory cells are programmed simultaneously.