NAND Flash Memory Over-Programming Prevention via Step-Up Voltage Control
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Solution Overview
Problem
Conventional NAND flash memories experience over-programming due to the biased states of adjacent memory cells during the writing process, leading to excessive writing voltage applied to memory cells, especially when writing to adjacent cells passes and fails in alternating bit line techniques.
Innovation Solution
A semiconductor memory device with a controller that adjusts the step-up voltage for write operations based on the write loop count, ensuring that the program voltage is stepped up only when necessary, thereby preventing excessive writing by controlling the potential of floating gates through capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If step-up writing is applied to ABL technique, then writing efficiency is improved, but over-programming occurs due to capacitive coupling from adjacent cell writing states
Solution Approach 1:
The patent applies preliminary anti-action by predicting the writing state of adjacent cells before performing step-up writing on the target cell. The controller checks whether adjacent cells are in a written or unwritten state, and only performs step-up writing when adjacent cells are in an unwritten state. This prevents the capacitive coupling effect that would otherwise cause over-programming, thereby maintaining threshold voltage distribution accuracy while preserving writing efficiency.
2Speed
If program voltage is stepped up for each write loop, then writing speed is improved, but floating gate potential increases excessively due to adjacent cell writing influence
Solution Approach 1:
The patent implements feedback by continuously monitoring the writing state of adjacent cells through sense amplifier outputs. The controller uses this feedback information to dynamically control whether step-up writing should be performed. When adjacent cells are detected to be in a written state, the controller suppresses step-up writing to prevent excessive floating gate potential increase. This feedback mechanism ensures writing accuracy is maintained while allowing speed optimization through step-up writing under appropriate conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents over-programming by restricting the potential increase of floating gates in memory cells, ensuring accurate data storage and maintaining the integrity of threshold voltage distributions, thus enhancing writing efficiency and accuracy.
Implementation Method 1
a potential of a floating gate of a memory cell of interest differs between when writing to an adjacent memory cell passes and when the writing to the adjacent memory cell does not passed. Specifically, when the writing does not pass, a channel for the adjacent cell is set to VSS. When the writing passes, the channel is set to a boost potential which is the VDD as an initial potential. Therefore, a potential of a floating gate of a memory cell for which writing to an adjacent memory cell passes is increased by capacitive coupling.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell array, a data memory circuit, a power generation circuit, and a controller. In the memory cell array, a plurality of memory cells which store two-or-more-bit data are arrayed in a matrix. When data is written to all memory cells connected to selected word lines, the controller performs a write operation with a write voltage obtained by adding the step-up voltage to the write voltage until a write count indicating a number of times by which writing is performed reaches a first write count. When the first write count is exceeded, the controller controls whether the step-up voltage is to be added or not, for each write operation.