NAND Flash P/E Cycle Count Tracking Using Select Gate Bits
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Solution Overview
Problem
Current NAND solid-state drive (SSD) technology faces challenges in accurately tracking program-erase (P/E) cycle counts due to space constraints in SRAM/DRAM, leading to compromised accuracy and granularity, and consumes capacitor energy during power loss.
Innovation Solution
A method for managing P/E cycle counts by updating bits in a memory system, specifically using a drain select gate (SGD) bit to represent different ranges of cycle counts, and storing these bits at locations other than user data cell blocks, allowing for efficient tracking and energy conservation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If P/E cycle counts are stored in SRAM or DRAM, then the memory system can track cycling counts, but it occupies relatively high amount space in the memory system
Solution Approach 1:
The patent extracts the P/E cycle count storage function from SRAM/DRAM and relocates it to non-volatile memory (NAND flash). By storing cycle counts in the memory array itself rather than in separate volatile memory, the system eliminates the need for dedicated SRAM/DRAM space while maintaining tracking capability.
Solution Approach 2:
The patent makes the NAND flash memory serve dual functions: storing user data and storing P/E cycle count information. The memory array is used universally for both data storage and metadata storage, eliminating the need for separate volatile memory resources.
2Area of stationary object
If P/E cycle counts are logged discretely or across each plane, then SRAM/DRAM space is saved, but the accuracy and granularity are highly compromised
Solution Approach 1:
The patent segments the P/E cycle count tracking into multiple independent counters, one for each memory plane. Each plane maintains its own accurate cycle count in the NAND memory, allowing precise tracking at the plane level without requiring centralized volatile memory storage.
Solution Approach 2:
The patent replaces the volatile memory-based counting mechanism with a non-volatile memory-based mechanism. By using NAND flash cells to store cycle counts directly, the system achieves both space efficiency and accuracy without the limitations of discrete logging approaches.
3Reliability
If capacitor energy is consumed to move controller information into NAND during power loss, then data is protected, but capacitor energy credit is consumed
Solution Approach 1:
The patent performs preliminary actions by continuously maintaining P/E cycle count information in the NAND memory during normal operation. This eliminates the need for emergency data movement during power loss events, as the critical information is already in non-volatile storage and protected from power loss without consuming capacitor energy.
Data Source
AI summary
This disclosure proposes a method to save P/E cycling information inside NAND by using 2-byte column in programmable selective devices (e.g., SGD). The proposed method is a one-way programming method, and does not perform an erase operation within the 2-byte column. The proposed methods described herein can reduce the burden of relying upon controller SRAM/DRAM. Additionally, by storing the P/E cycling information in NAND, the P/E cycling is not lost due to a power loss event. At least one application advantageous for using NAND to store P/E cycling information includes wear leveling.