NAND Flash Page Copy via Concurrent Read and Arithmetic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current NAND flash memory devices require additional time for page copy operations due to the separate execution of data read and arithmetic operations for converting input data to write data, which prolongs the overall process.
Innovation Solution
The semiconductor memory device incorporates a control circuit that performs arithmetic operations for converting input data to write data during the data read operation, reducing the time needed for page copy by executing these operations concurrently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data read and arithmetic operations for converting input data to write data are executed separately, then the page copy operation can be completed with clear sequential steps, but the overall time required for page copy operation increases
Solution Approach 1:
The patent merges the data read operation and the arithmetic operation for converting input data to write data into a single concurrent execution phase. The control circuit is designed to perform both operations simultaneously, eliminating the sequential execution delay and reducing the total time required for page copy operations.
Solution Approach 2:
The control circuit prepares and executes the arithmetic operation for data conversion during the data read operation itself, rather than waiting for the read operation to complete. This preliminary action allows the conversion process to start earlier, overlapping with the read operation and reducing overall execution time.
2Productivity
If arithmetic operations are executed during data read operation, then the time for page copy is reduced, but the control circuit must manage concurrent operations increasing its complexity
Solution Approach 1:
The control circuit is designed with multi-functionality to handle both data read operations and arithmetic conversion operations within the same circuit architecture. This universal design allows the control circuit to manage concurrent operations without requiring separate dedicated circuits, thus improving page copy speed while controlling complexity growth.
Solution Approach 2:
The control circuit maintains continuous useful action by ensuring that the arithmetic operation for data conversion proceeds continuously during the data read operation without idle periods. This continuous execution maximizes productivity by eliminating gaps between operations and keeping the control circuit fully utilized throughout the page copy process.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, first and second data caches, and a control circuit. The control circuit is configured to control, with use of the first and second data caches, a read operation of reading data from the selected memory cell of the memory cell array, and a write operation of writing data in the selected memory cell of the memory cell array. The control circuit is configured to execute, at a time of the read operation, an arithmetic operation of the data held in the first data cache by using the first and second data caches, and to generate the data which is to be written in the selected memory cell.