NAND Flash Page Mapping for Smaller Internal Page Sizes
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Solution Overview
Problem
Existing semiconductor memories, particularly NAND flash memories, face challenges in efficiently managing and converting between logical and physical page addresses, leading to inefficiencies in data storage and retrieval operations.
Innovation Solution
A semiconductor memory system that includes a memory controller and a NAND flash memory, where the memory controller converts one external address into multiple internal addresses, allowing for smaller page sizes to be managed efficiently, and a circuit that converts logical page addresses to physical page addresses, enabling better data allocation and operation management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of sense amplifier units and latch circuits is reduced, then chip area is reduced, but processing speed may be affected
Solution Approach 1:
The patent divides logical pages into multiple physical pages, allowing data to be distributed across fewer sense amplifier units and latch circuits. This segmentation enables parallel processing of data subsets while reducing the total number of peripheral circuit units required, thus decreasing chip area without significantly impacting overall processing speed.
2Quantity of substance
If memory cell transistors are miniaturized, then storage capacity per unit area increases, but peripheral circuit area does not reduce proportionally
Solution Approach 1:
By segmenting logical pages into multiple physical pages with smaller individual page sizes, the patent reduces the data width required for each peripheral circuit unit. This allows memory cell transistors to be miniaturized more effectively while keeping peripheral circuit area proportional to the reduced page size rather than total storage capacity.
Solution Approach 2:
The patent introduces a new dimension of data organization by mapping logical pages to multiple physical pages across different memory blocks. This dimensional transformation allows efficient utilization of miniaturized memory cells while maintaining manageable peripheral circuit requirements through distributed data storage.
3Productivity
If page size is reduced to fit more data in parallel, then processing throughput increases, but chip area increases due to more peripheral circuits
Solution Approach 1:
The patent segments large logical pages into smaller physical pages, enabling efficient parallel processing with reduced peripheral circuit requirements. By processing multiple smaller physical pages in parallel rather than one large logical page, the system achieves high throughput while keeping the area of individual peripheral circuit units small.
Data Source
AI summary
According to one embodiment, a semiconductor memory includes: a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states; a word line coupled to the plurality of memory cells; and a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein a first page size of page data of the memory group is smaller than a second page size of input data corresponding to the external address.