NAND Flash Programming Pulse Scheme for Threshold Voltage Stability
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Solution Overview
Problem
The rapid charge loss in NAND flash memory cells leads to initial threshold voltage shift and broadening of threshold voltage distribution curves, resulting in lower reliability due to device size reduction and multi-value storage demands.
Innovation Solution
A two-step programming method is employed, where a first programming operation applies a one-pulse to program memory cells into N states without verification, followed by a second operation using incremental step pulse programming to achieve target states, thereby mitigating the effects of rapid charge loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced and multi-value storage technology is adopted to increase storage capacity, then storage density is improved, but initial threshold voltage shift becomes more severe and reliability decreases
Solution Approach 1:
The patent segments the programming process into two distinct phases: a first programming operation that programs memory cells to intermediate states, and a second programming operation that adjusts cells to final target states. This segmentation allows the system to handle the reliability issues caused by rapid charge loss by treating different groups of cells with different programming strategies, thereby maintaining high storage capacity while improving reliability.
Solution Approach 2:
The first programming operation serves as a preliminary action that programs all selected memory cells to intermediate states before the second programming operation refines them to final states. This preliminary programming establishes a baseline state for all cells, and subsequent verification and adjustment operations can then focus on correcting specific cells that suffer from rapid charge loss, thereby improving overall reliability without sacrificing storage density.
2Reliability
If rapid charge loss is mitigated through multiple programming operations and verification, then reliability is improved, but programming time increases
Solution Approach 1:
The patent applies partial verification in the first programming operation, verifying only certain groups of memory cells rather than all cells. This partial action approach maintains reliability by verifying critical cells while avoiding the time penalty of verifying every single cell, thus balancing reliability improvement with programming time constraints.
Solution Approach 2:
The programming process uses periodic verification operations interspersed between programming pulses. Instead of continuous verification, the system performs verification at specific intervals and for specific cell groups, which reduces the overall programming time while still catching and correcting cells affected by rapid charge loss, thereby maintaining reliability.
Data Source
AI summary
The present disclosure provides a method of operating a memory, a memory, a memory system and an electronic device. In an example, a method of operating a memory is provided. The memory includes multiple word lines, and each of the plurality of word lines is coupled to a plurality of memory cells. The method includes: performing a first programming operation on a plurality of memory cells coupled to a selected word line among the multiple word lines, the first programming operation including applying a one-pulse to the selected word line to program the multiple memory cells coupled to the selected word line into N programmed states; and performing a second programming operation on the selected word line to program the multiple memory cells coupled to the selected word line into N target programmed states, where N is a positive integer.