NAND Flash Memory Cell Read Disturb Compensation
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Solution Overview
Problem
In NAND flash memory devices, parasitic capacitance coupling between adjacent floating gates causes floating gate-to-floating gate interference, leading to wider threshold voltage distributions and degraded programming performance, especially in multi-level cell arrays where the differences between adjacent threshold voltage distributions are small, resulting in increased interference effects.
Innovation Solution
The method involves performing a read operation on an adjacent cell to determine if a target cell is in a disturbed condition due to floating gate-to-floating gate interference, and adjusting the sensing parameter, such as precharge bit line voltage or sensing time, to compensate for the interference, allowing accurate data reading by treating disturbed cells as though they have undisturbed voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multilevel memory cells are used to increase storage density, then memory density is improved, but floating gate-to-floating gate interference increases causing wider threshold voltage distributions
Solution Approach 1:
The patent performs a preliminary read operation on adjacent memory cells before reading the target cell. This preliminary action detects potential floating gate interference from adjacent cells, allowing the system to prepare appropriate compensation measures (such as adjusting reference voltages or sensing parameters) before the actual read operation, thereby preventing read errors caused by interference.
Solution Approach 2:
The patent implements a feedback mechanism where the read operation on adjacent cells provides information about the interference state. Based on this feedback, the system adjusts sensing parameters or reference voltages for reading the target cell, creating a closed-loop system that compensates for floating gate interference and maintains accurate data retrieval.
2Adaptability or versatility
If adjacent memory cells are programmed after a target cell, then memory writing flexibility is improved, but floating gate interference distorts the target cell's threshold voltage
Solution Approach 1:
The system performs a preliminary read operation on adjacent cells before reading the target cell to detect potential interference. This preliminary detection allows the system to identify cells that have been programmed after the target cell and are causing floating gate interference, enabling appropriate compensation before the actual data read operation.
Solution Approach 2:
The read operation on adjacent cells provides feedback information about their programmed state and potential interference. This feedback is used to adjust the reading parameters for the target cell, such as modifying reference voltages or sensing thresholds, thereby compensating for the floating gate interference and maintaining reliable data retrieval.
3Manufacturing precision
If floating gate-to-floating gate coupling is reduced through cell spacing, then interference is decreased, but memory array density decreases
Solution Approach 1:
The patent introduces an intermediary measurement step - reading adjacent cells to detect interference levels. This intermediary action serves as a mediator between the physical interference phenomenon and the data reading process, allowing the system to detect and compensate for floating gate coupling effects without requiring increased physical spacing between cells, thereby maintaining high memory density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces or prevents read errors by compensating for threshold voltage shifts caused by floating gate-to-floating gate interference, ensuring accurate data retrieval in multilevel memory cells.
Implementation Method 1
parasitic capacitance coupling between adjacent memory cell floating gates becomes a problem. Floating gate-to-floating gate interference can cause a wider Vt distribution
Data Source
AI summary
Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition.