NAND Flash Read-Level Correction for Threshold Voltage Overlap

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Solution Overview

Problem

Existing memory systems face challenges in accurately reading data due to variations in threshold voltage distributions of memory cells, leading to errors and incorrect data retrieval, particularly in NAND flash memories, as adjacent distributions overlap and cause misinterpretation of stored data.

Innovation Solution

The memory system employs a dynamic shift value calculation for adjusting read levels based on error detection during read operations, utilizing a correction amount calculation circuit to determine a suitable read level by offsetting standard levels, thereby improving data reading accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If standard read levels are used for reading data from memory cells, then the reading operation is simple and fast, but data reading accuracy deteriorates due to threshold voltage variations and overlapping distributions

Engineering Contradiction:
Improvedata reading accuracyVSAvoidread level adjustment mechanism
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements dynamic read level adjustment by calculating correction amounts based on detected errors during read operations. The read level is not fixed but dynamically modified according to the specific characteristics and error patterns of each memory cell or block, allowing the system to adapt to threshold voltage variations and overlapping distributions in real-time

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms where the memory controller detects errors during read operations and uses this information to calculate correction amounts. These corrections are fed back to adjust the read levels for subsequent operations, creating a closed-loop system that continuously improves reading accuracy based on actual performance data

Inventive Principle:
Principle #23Feedback

2Measurement precision

If multiple read levels are tested to determine threshold voltages, then data reading accuracy improves, but read operation time increases

Engineering Contradiction:
Improvethreshold voltage determination accuracyVSAvoidread operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary characterization operations during manufacturing or initial setup to establish baseline read levels and error detection mechanisms. By preparing correction tables and calibration data in advance, the system can quickly apply corrections during actual read operations without needing to perform time-consuming multiple-level testing in real-time

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the read level parameter dynamically based on calculated correction amounts rather than testing multiple fixed levels. This allows the system to achieve high accuracy by adjusting a single optimal read level for each memory cell or block, avoiding the time consumption of sequentially testing multiple predetermined levels

Inventive Principle:
Principle #35Parameter changes

3Reliability

If error detection is performed during read operations, then data reliability improves, but processing complexity increases

Engineering Contradiction:
Improvedata retrieval reliabilityVSAvoiderror detection and correction mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service error detection where the memory device itself performs error detection and correction using built-in circuits and mechanisms. The memory cells and control circuits autonomously detect errors and apply corrections without requiring external intervention or complex additional processing systems, reducing overall system complexity while maintaining high reliability

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20260080955A1Memory system and memory device
Publication Date: 2026.03.19 KIOXIA CORP
  • US20260080955A1 patent drawing
  • US20260080955A1 patent drawing
  • US20260080955A1 patent drawing

AI summary

According to one embodiment, a memory system includes: a memory device including memory cells for storing data; and a memory controller configured to control an operation of the memory device, wherein the memory device is configured to: acquire, in response to a first read command set, a first determination result of threshold voltages of the memory cells based on a first read level related to a first threshold voltage distribution and a second determination result of threshold voltages of the memory cells based on a first lower-voltage side offset read level, the first lower-voltage side offset read level is obtained by offsetting the first read level to a lower-voltage side, acquire a first number of mismatches between the first determination result and the second determination result, and calculate a first correction amount of the first read level based on the first number of mismatches.