NAND Flash Memory Read Pass Voltage Adjustment for Interference
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Solution Overview
Problem
The existing three-stage and two-stage programming systems in NAND flash memory devices face challenges in managing interference effects between cells, leading to shifts in threshold distributions and errors during data read operations, particularly with the ER level transitioning to positive voltage sides due to programming intensity variations.
Innovation Solution
The semiconductor memory device employs a read sequence that adjusts the read pass voltage applied to neighboring word lines based on the interference effect intensity, grouping memory cells according to the programming stage of neighboring cells, and using multiple read levels to correct threshold voltage shifts, thereby enhancing data read accuracy and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If programming intensity is increased to improve data write speed, then productivity is improved, but threshold distribution shifts occur causing read errors
Solution Approach 1:
The patent applies preliminary action by performing a read-disturb compensation operation before the actual data read. The control circuit first determines if a read-disturb condition exists based on programming intensity, and if so, compensates for the threshold shift by adjusting the read pass voltage on neighboring word lines before reading the target data, thereby preventing read errors caused by high-speed programming
Solution Approach 2:
The patent implements feedback by monitoring programming intensity during the programming operation and using this information to dynamically adjust subsequent read operations. The control circuit receives programming intensity information, determines read-disturb conditions based on this feedback, and adjusts read pass voltages accordingly to maintain data read accuracy even when programming speed varies
2Measurement precision
If read pass voltage is increased to improve signal detection, then measurement precision is improved, but interference effects between cells worsen
Solution Approach 1:
The patent applies local quality by differentiating the read pass voltage application based on cell group and interference condition. Instead of uniformly increasing voltage across all cells, the control circuit selectively adjusts read pass voltage only on neighboring word lines where interference is detected, while maintaining normal voltage on non-affected cells, thereby improving signal detection without unnecessarily increasing interference
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the read pass voltage parameter based on detected interference conditions. The control circuit changes the voltage parameter from a standard level to a compensated level when read-disturb conditions are detected, allowing optimal signal detection while minimizing unnecessary interference effects
3Manufacturing precision
If threshold distribution width is reduced to improve manufacturing precision, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by implementing automatic read-disturb compensation that operates autonomously based on programming intensity detection. The control circuit automatically determines when compensation is needed and executes the appropriate voltage adjustments without requiring external intervention or complex manual calibration, thereby maintaining threshold distribution control while limiting complexity increase to only the necessary automatic detection and adjustment functions
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a control circuit, during data write to a memory cell, sequentially executing: an erasing stage in which a threshold value of the memory cell is transitioned into an erase distribution; a preliminary programming stage in which the threshold value is transitioned into a temporal distribution corresponding to write data; and a main programming stage in which the threshold value is transitioned into a program distribution corresponding to the write data, and the control circuit executing a main reading stage, during the data read to a first memory cell, which includes a main reading step of adjusting a read pass voltage to be applied to a neighboring word line based on a magnitude of a threshold value of the neighboring memory cell, and reading whether the first memory cell is an erase level.