NAND Flash Memory Bank With Segmented Well Sectors
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Solution Overview
Problem
Prior NAND flash memory technologies face challenges in achieving high-speed erase performance while minimizing charge pump circuit area, power consumption, and erase stress for unselected memory blocks, due to large well sectors and capacitance, which affects erase time and reliability.
Innovation Solution
The solution involves forming NAND flash memory banks with multiple well sectors, each containing one or more memory blocks, where only selected well sectors receive the erase voltage, reducing capacitance and allowing for faster erase operations with a smaller charge pump circuit, and using isolation devices to decouple bitline segments during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single large well sector is used to contain all memory blocks, then the memory array can be compactly organized, but the capacitance of the well sector becomes large, resulting in slow erase speeds and high power consumption
Solution Approach 1:
The memory array is divided into multiple well sectors (first well sector, second well sector, etc.), each containing one or more memory blocks. This segmentation allows the erase voltage to be applied to only the selected well sector containing the target memory block, rather than charging the entire large well sector. The reduced capacitance of individual well sectors enables faster erase speeds and lower power consumption while maintaining compact memory array organization.
2Reliability
If the erase voltage is applied to all well sectors simultaneously, then all memory blocks can be erased in parallel, but unselected memory blocks receive unnecessary erase stress, reducing reliability
Solution Approach 1:
The memory array is segmented into multiple well sectors that can be independently controlled. During erase operations, only the selected well sector containing the target memory block receives the erase voltage, while other well sectors remain unaffected. This selective erasure eliminates unnecessary erase stress on unselected memory blocks, improving reliability and data retention.
Solution Approach 2:
The system dynamically selects and activates only the specific well sector containing the memory block to be erased, rather than statically erasing all well sectors simultaneously. This dynamic control allows for targeted erasure operations that improve reliability by avoiding unnecessary stress on unselected blocks while maintaining efficient erase throughput through precise address decoding and well sector selection.
3Area of stationary object
If a large charge pump circuit is used to provide erase voltage to the entire memory array, then all memory blocks can be erased, but the charge pump occupies large chip area and consumes excessive power
Solution Approach 1:
The memory array is divided into multiple well sectors, each with its own isolated bitline segment. This segmentation allows the charge pump circuit to supply erase voltage to only one well sector at a time, rather than requiring simultaneous voltage supply to the entire memory array. The reduced capacitance load enables the use of a smaller charge pump circuit that occupies less chip area and consumes less power during erase operations.
Solution Approach 2:
Isolation devices are introduced as intermediaries between bitline segments of different well sectors. These isolation devices prevent voltage coupling between well sectors, allowing the charge pump to efficiently charge only the selected well sector's bitline segment without charging other segments. This intermediary isolation mechanism reduces the effective capacitance that the charge pump must charge, enabling smaller charge pump design with lower power consumption.
4Speed
If bitline segments of different well sectors are coupled together, then the memory array can be accessed uniformly, but during erase operations the capacitance increases, slowing down erase speed
Solution Approach 1:
The bitline structure is segmented into separate bitline segments for each well sector, with isolation devices positioned between segments. During erase operations, the isolation devices are activated to decouple the bitline segments, preventing capacitance coupling between well sectors. This segmentation allows the erase voltage to be applied rapidly to the selected well sector without the capacitance burden of other well sectors, significantly improving erase speed.
Solution Approach 2:
The isolation devices are dynamically controlled based on the erase operation requirements. During normal read/write operations, the isolation devices are in the on-state to allow uniform memory array access. During erase operations, the isolation devices are switched to the off-state to decouple bitline segments and enable fast erase. This dynamic control strategy balances the trade-off between operational uniformity and erase speed, with the added complexity being manageable through simple control logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster erase speeds, reduced power consumption, and minimized erase stress on unselected memory blocks, while maintaining or improving erase performance and reducing chip area and cost.
Implementation Method 1
reducing capacitance and allowing for faster erase operations with a smaller charge pump circuit
Implementation Method 2
using isolation devices to decouple bitline segments during erase operations
Data Source
AI summary
A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.