NAND Flash Select-Line Voltage Control for Leakage Suppression

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Solution Overview

Problem

NAND-type flash memory experiences increased leakage current and hot carriers in non-conductive select transistors during data read operations, which affect the reliability and efficiency of the memory device.

Innovation Solution

A semiconductor memory device is designed with a driver module that applies a difference in voltages to selection lines, ensuring that non-selected select transistors remain in a non-conductive state by using a first non-selection voltage for some transistors and a second non-selection voltage for others, thereby reducing leakage current and hot carriers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If select transistors are used in NAND-type flash memory for data read operations, then data read capability is improved, but leakage current and hot carriers increase in non-conductive select transistors

Engineering Contradiction:
Improvedata read capabilityVSAvoidleakage current and hot carriers
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The selection lines are divided into multiple groups (first selection lines and second selection lines) corresponding to different string units. By segmenting the control structure, the patent applies different voltage levels to different groups of select transistors, allowing selective suppression of leakage current and hot carriers in non-conductive transistors while maintaining read capability in selected transistors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different voltage levels (first non-selection voltage and second non-selection voltage) are applied to different groups of select transistors based on their specific operational state and position. This local differentiation in voltage application optimizes each group's performance, minimizing leakage and hot carriers in non-selected transistors while preserving read functionality in selected transistors.

Inventive Principle:
Principle #3Local quality

2Device complexity

If non-conductive select transistors are maintained in a single voltage state, then device complexity is reduced, but leakage current and hot carriers cannot be effectively minimized

Engineering Contradiction:
Improvevoltage control structureVSAvoidleakage current and hot carriers
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The voltage control system is segmented into multiple levels (first non-selection voltage and second non-selection voltage) applied to different groups of select transistors. This segmentation enables differentiated control without requiring complex individual control for each transistor, achieving effective leakage and hot carrier suppression through grouped voltage application.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the voltage parameter applied to select transistors based on their selection state and group assignment. By introducing multiple voltage levels (first non-selection voltage and second non-selection voltage) instead of a single voltage state, the system effectively controls leakage current and hot carriers while maintaining manageable device complexity through systematic parameter differentiation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260045306A1Semiconductor memory device and method of driving semiconductor memory device
Publication Date: 2026.02.12 KIOXIA CORP
  • US20260045306A1 patent drawing
  • US20260045306A1 patent drawing
  • US20260045306A1 patent drawing

AI summary

A semiconductor memory device includes strings each including memory cells connected in series; first select transistors connected to one end of the strings; second select transistors connected to the other end of the strings; first control lines commonly provided to the strings and connected to gates of the memory cells; first selection lines connected to gates of the first select transistors and each corresponding to a first unit having one string; second selection lines connected to gates of the second select transistors and corresponding to a second unit including a plurality of the first units; and a driver configured to provide a voltage for the plurality of first selection lines, causing a difference between a first non-selection voltage and a second non-selection voltage.