NAND Flash Memory Write Cycle Optimization via Source Line Voltage Control

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Solution Overview

Problem

The programming of data into non-volatile memories is a time, current, and power-consuming operation, particularly due to the need for alternating series of programming and verify operations in flash EEPROM devices, which limits the efficiency and speed of write operations.

Innovation Solution

A method and circuitry for programming non-volatile memory cells in a NAND type architecture that involves biasing bit lines and a common source line to specific voltage levels during pulse and verify operations, with subsequent equalization of these levels to reduce the time and power required for each cycle, allowing for efficient recycling of charge and minimizing discharge and pre-charge times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If alternating series of programming and verify operations are performed, then data programming reliability is improved, but write operation time and power consumption increase

Engineering Contradiction:

Improvedata programming reliabilityVSAvoidwrite operation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The source line is pre-charged to a non-zero voltage level before the programming pulse is applied. This preliminary action eliminates the need to discharge and re-charge the source line between programming and verify operations, reducing the time required for each cycle while maintaining programming reliability.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention changes the voltage parameter of the source line from zero to a non-zero level during verify operations. This parameter change allows the verify operation to proceed without the time-consuming discharge and re-charge cycle, thereby reducing overall write operation time while preserving data programming reliability through proper voltage level management.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If alternating series of programming and verify operations are performed, then data programming reliability is improved, but power consumption increases

Engineering Contradiction:

Improvedata programming reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

By changing the source line voltage parameter to a non-zero level and maintaining it during verify operations, the invention eliminates repeated charge-discharge cycles. This reduces the energy consumed by the source line driver and minimizes current leakage, thereby reducing overall power consumption while maintaining programming reliability.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The invention converts what would normally be harmful current leakage and energy waste during source line discharge into a beneficial state by maintaining a sustained non-zero voltage level. This eliminates the harmful discharge-recharge cycle, reducing power consumption while preserving the necessary verify functionality for reliable programming.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Object-generated harmful factors

If source line is discharged to zero between operations, then bit line coupling is minimized, but discharge and pre-charge time increases

Engineering Contradiction:

Improvebit line couplingVSAvoiddischarge and pre-charge time

Core Design Contradiction:

Object-generated harmful factorsVSLoss of time

Solution Approach 1:

The source line is pre-charged to a non-zero voltage level before programming operations begin and maintains this level during verify operations. This preliminary and sustained action eliminates the need for time-consuming discharge and re-charge cycles between operations, reducing overall operation time while managing bit line coupling through controlled voltage levels.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention dynamically adjusts the source line voltage to maintain a non-zero level during verify operations rather than statically discharging to zero. This dynamic approach allows the system to minimize bit line coupling through controlled voltage management while avoiding the time penalty of repeated discharge and pre-charge cycles.

Inventive Principle:

Principle #15Dynamics

4Speed

If source line is maintained at non-zero voltage during verify, then operation speed is improved, but current leakage increases

Engineering Contradiction:

Improveoperation speedVSAvoidcurrent leakage

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The invention optimizes the voltage parameter of the source line to a specific non-zero level that balances speed and power consumption. By carefully selecting and maintaining this voltage level during verify operations, the system achieves improved operation speed while minimizing current leakage through precise voltage control.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8842471B2Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: program to verify transition

Publication Date: 2014.09.23 SANDISK TECHNOLOGIES LLC

AI summary

In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.