NAND Flash Controller Read Voltage Lookup Table for Retention Degradation
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Solution Overview
Problem
NAND flash memory-based storage devices experience reliability degradation due to frequent operations and environmental factors, leading to increased raw bit error rates and read latency, as the threshold voltage distribution shifts, causing misread errors that exceed error correction capabilities.
Innovation Solution
A method is introduced where a controller loads a look-up table containing first and second read reference voltage sets, corresponding to retention degradation stages, to adjust read reference voltages dynamically, ensuring accurate discrimination between threshold voltage states, thereby reducing read errors and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read reference voltages are adjusted dynamically based on retention degradation stages, then read accuracy is improved, but device complexity increases
Solution Approach 1:
The patent pre-calculates and stores multiple sets of read reference voltages corresponding to different retention degradation stages in a lookup table before actual operation. During read operations, the controller simply retrieves the appropriate voltage set based on the current retention stage, avoiding complex real-time calculations and reducing operational complexity while maintaining high read accuracy
Solution Approach 2:
The patent implements dynamic adjustment of read reference voltages by selecting different voltage sets from the lookup table based on the current retention degradation stage. This allows the system to adapt to changing memory characteristics over time, improving read accuracy as the memory ages without requiring complex real-time analysis
2Reliability
If multiple read reference voltage sets are stored in lookup table, then read errors are reduced, but memory usage increases
Solution Approach 1:
The patent segments the read reference voltage data into multiple distinct sets, each corresponding to a specific retention degradation stage. This segmentation allows the system to store voltages in an organized manner in the lookup table, efficiently utilizing memory space while providing targeted voltage adjustments for different operational conditions, thereby reducing read errors without excessive memory consumption
3Loss of time
If read reference voltages are adjusted for retention degradation, then read latency is reduced, but processing complexity increases
Solution Approach 1:
The patent determines the current retention degradation stage and loads the corresponding read reference voltage set from the lookup table in advance, before actual read operations begin. This preliminary preparation ensures that the most appropriate voltage set is already available when reads are needed, minimizing read latency without requiring complex real-time voltage adjustment during the read process itself
Data Source
AI summary
Disclosed is a method of operating a storage device including a NAND flash memory including memory cells grouped into blocks, each block being divided into pages. According to the method, a controller in the storage device loads, onto a memory region, a look-up table containing first read reference voltage sets corresponding to respective retention degradation stages of the NAND flash memory and second read reference voltages sets corresponding to respective pages which vary in terms of the threshold voltages. Subsequently, the controller performs a read operation on the memory cells on a per-block basis by using the first read reference voltage set corresponding to a current retention degradation stage, the second read reference voltage set corresponding to a current page, or both, until all of the memory cells in a current block are correctly read.