NAND Flash Memory Voltage Control for Write Inhibition

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Solution Overview

Problem

Conventional NAND flash memory techniques, such as self-boost schemes, often result in excessive voltage being applied to unselected word lines, leading to erroneous writing in memory cells connected to them.

Innovation Solution

A semiconductor memory device and method where a driver circuit applies a first voltage to selected word lines and a second voltage to unselected word lines, with the control circuit stepping up the first voltage and keeping the second voltage constant until the first voltage reaches a threshold, then increasing the second voltage, preventing erroneous writing by managing the potential difference between the control gate and channel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If voltage is stepped up to unselected word lines to prevent electron injection, then write inhibition is improved, but erroneous writing to connected memory cells occurs

Engineering Contradiction:
Improvewrite inhibitionVSAvoiderroneous writing
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent dynamically adjusts the voltage applied to unselected word lines based on the programming state. Initially, a lower voltage is applied during early programming iterations, and only after the selected memory cell reaches sufficient threshold voltage does the voltage to unselected word lines increase. This dynamic adjustment prevents erroneous writing while maintaining write inhibition effectiveness.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies a preliminary lower voltage to unselected word lines before the selected memory cell completes its programming. This preliminary action prevents electrons from being injected into the charge accumulation layer of unselected cells during the critical early programming phases, avoiding erroneous writing before the inhibition mechanism is fully established.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If voltage is repeatedly applied to selected word line for programming, then data writing is achieved, but excessive voltage increase causes erroneous writing

Engineering Contradiction:
Improveprogramming speedVSAvoidwrite accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements dynamic voltage control where the voltage applied to unselected word lines changes based on the programming iteration count and the state of the selected memory cell. This allows rapid programming of selected cells while dynamically preventing erroneous writing to unselected cells throughout the programming process.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses feedback from the programming process to adjust voltages. By monitoring whether the selected memory cell has reached the desired threshold voltage, the system adjusts the voltage applied to unselected word lines accordingly, ensuring write accuracy is maintained throughout repeated programming operations.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the operational reliability of NAND flash memory by preventing data from being erroneously written to unselected cells, reducing the potential difference between the control gate and channel, and avoiding excessive increases in voltage.

Implementation Method 1

a self-boost scheme is commonly used which increases the channel potential of a write inhibited cell through coupling to a gate potential to prevent electrons from being injected into a charge accumulation layer in the cell

Methodology Applied
Scientific EffectElectrostatic coupling: Electrostatic Induction

Data Source

PatentUS8369153B2Semiconductor memory device including stacked gate having charge accumulation layer and control gate and method of writing data to semiconductor memory device
Publication Date: 2013.02.05 KIOXIA CORP
  • US8369153B2 patent drawing
  • US8369153B2 patent drawing
  • US8369153B2 patent drawing

AI summary

A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.