3D NAND Gate Contact Structure for Reliable Vertical Memory Stacks
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and achieving improved electrical properties and reliability, particularly in manufacturing efficiency and performance.
Innovation Solution
A semiconductor device design featuring a substrate with vertically stacked gate electrodes, interlayer insulating layers, channel structures, and sacrificial insulating patterns, including boron, to enhance electrical connectivity and reliability, allowing for increased data storage capacity and efficient manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed three-dimensionally to increase data storage capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking of gate electrodes and memory cells vertically. Multiple gate electrodes are stacked in the vertical direction with interlayer insulating layers between them, enabling increased storage capacity by utilizing the third dimension (height) rather than only expanding in the planar area.
Solution Approach 2:
The memory device is segmented into multiple functional layers including first gate electrodes, second gate electrodes, channel structures, and interlayer insulating layers. Each layer performs a specific function, and the segmented structure allows for systematic organization and manufacturing of the three-dimensional architecture.
2Quantity of substance
If gate electrodes are stacked vertically to increase storage capacity, then data storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
Interlayer insulating layers are formed between the first and second gate electrodes before the final stacking process. This preliminary formation of insulating layers provides a stable foundation and alignment reference for subsequent gate electrode stacking, reducing the precision requirements for the final assembly process.
Solution Approach 2:
Interlayer insulating layers act as intermediary elements between the first and second gate electrodes. These insulating layers facilitate the stacking process by providing electrical isolation, mechanical support, and alignment guidance, thereby reducing the direct precision requirements between adjacent gate electrodes.
3Reliability
If gate contact plugs are spaced apart from lower gate electrodes, then electrical reliability is improved, but device complexity increases
Solution Approach 1:
The gate contact plug is extracted from direct contact with the lower gate electrode and positioned spaced apart from it. This separation prevents potential electrical interference and reliability issues that would arise from direct contact, while the contact plug still maintains its function of providing electrical connection to the upper gate electrode through the insulating layers.
Data Source
AI summary
A semiconductor device including gate electrodes stacked and spaced apart from each other in a first direction, extending by different lengths in a second direction on the second region, and each including a pad region having an upper surface exposed upwardly in the second region and a stack region other than the pad region, the gate electrodes including a first gate electrode and a second gate electrode below the first gate electrode, a first contact plug insulating layer on interlayer insulating layers in the pad region of the first gate electrode, surrounding a gate contact plug, and vertically overlapping the first gate electrode, second contact plug insulating layers alternating with the interlayer insulating layers below the pad region of the first gate electrode and surrounding the gate contact plug may be provided.