3D NAND Memory Gate Stack With Metal Oxide Diffusion Barrier
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Solution Overview
Problem
Current three-dimensional NAND flash memory devices face challenges in maintaining charge retention characteristics due to impurity diffusion from gate electrode layers, leading to leakage currents and reduced data storage reliability.
Innovation Solution
Incorporating a metal oxide layer containing titanium (Ti), molybdenum (Mo), tungsten (W), or tantalum (Ta) between the second block insulating layer and the gate electrode layer, which suppresses impurity diffusion and enhances charge retention by forming a barrier that prevents current leakage between the charge storage layer and the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional three-dimensional NAND flash memory structure is used, then high integration and low cost are achieved, but impurity diffusion occurs between the charge storage layer and gate electrode layer, degrading charge retention and erase saturation characteristics
Solution Approach 1:
A metal oxide layer is introduced as an intermediary barrier between the charge storage layer and gate electrode layer. This metal oxide layer specifically suppresses impurity diffusion while allowing the memory device to maintain its three-dimensional stacked structure and manufacturing simplicity.
Solution Approach 2:
The patent employs a composite structure combining multiple materials including the metal oxide layer, charge storage layer, block insulating layers, and gate electrode layer. This composite material approach enables simultaneous achievement of impurity suppression, charge retention, and structural integrity in the memory device.
2Reliability
If the metal oxide layer is added to suppress impurity diffusion, then charge retention characteristics improve, but device structure becomes more complex
Solution Approach 1:
The metal oxide layer is selectively positioned only where impurity diffusion occurs between the charge storage layer and gate electrode layer. This localized approach improves erase saturation characteristics without unnecessarily complicating the entire device structure, adding complexity only where functionally required.
Solution Approach 2:
The insulating layer is segmented into multiple functional layers including the metal oxide layer, charge storage layer, and block insulating layers. This segmentation allows each layer to perform its specific function independently, improving overall device performance while maintaining a systematic and manageable structural organization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves charge retention characteristics and erase saturation performance by reducing impurity diffusion, thereby enhancing the overall data storage reliability and efficiency of the semiconductor memory device.
Implementation Method 1
a metal oxide layer provided between the third insulating layer and the gate electrode layer and containing at least one first metal element selected from a group consisting of titanium (Ti), molybdenum (Mo), tungsten (W), and tantalum (Ta)
Implementation Method 2
a metal nitride layer provided between the second block insulating layer and the metal oxide layer and containing at least one second metal element selected from a group consisting of titanium (Ti), molybdenum (Mo), tungsten (W), and tantalum (Ta)
Data Source
AI summary
A semiconductor memory device of an embodiment includes: a semiconductor layer extending in a first direction; a gate electrode layer containing at least one element selected from a group consisting of molybdenum (Mo), tungsten (W), ruthenium (Ru), and cobalt (Co); a first insulating layer provided between the semiconductor layer and the gate electrode layer; a charge storage layer provided between the first insulating layer and the gate electrode layer; a second insulating layer provided between the charge storage layer and the gate electrode layer; a third insulating layer provided between the second insulating layer and the gate electrode layer; and a metal oxide layer provided between the third insulating layer and the gate electrode layer and containing at least one first metal element selected from a group consisting of titanium (Ti), molybdenum (Mo), tungsten (W), and tantalum (Ta).