NAND Memory Inversion Bit Lines for Cell Size Reduction
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Solution Overview
Problem
Conventional NAND memory devices are limited in size reduction due to the necessity of implanted bit lines, which occupy space and restrict the miniaturization of memory cells.
Innovation Solution
The use of inversion bit lines eliminates the need for implanted bit lines, allowing for reduced cell size and increased density in NAND memory devices by using polysilicon regions to create inversion bit lines that conduct source and drain voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If implanted bit lines are used in conventional NAND memory devices, then the device can function properly with source and drain voltage conduction, but the cell size is increased and density is reduced
Solution Approach 1:
The patent extracts and eliminates the implanted bit lines from the memory cell structure. By removing these physical conductive lines that occupy space, the invention reduces cell area while maintaining voltage conduction through an alternative mechanism (inversion layer formation in the substrate), directly resolving the contradiction between reliability and cell size
Solution Approach 2:
The patent replaces the mechanical/physical implanted bit line structure with an electrical field-based inversion layer mechanism. Instead of using physical conductive paths through implanted regions, the invention uses electric field-induced inversion layers to conduct voltages, substituting a physical structure with a field-based mechanism that requires less space
2Productivity
If cell size is reduced to increase density, then higher density and smaller packaging are achieved, but the implanted bit lines cannot be accommodated
Solution Approach 1:
By extracting the implanted bit lines from the cell structure, the patent removes the manufacturing constraint that limited cell size reduction. This extraction enables smaller cell dimensions and higher density while simplifying the manufacturing process by eliminating the complex implanted bit line formation steps
Solution Approach 2:
The invention changes the fundamental parameter of voltage conduction from physical wire-based conduction to field-induced inversion layer conduction. This parameter change enables scaling to smaller dimensions while maintaining functionality, directly supporting higher density and improved manufacturability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of smaller, higher density NAND memory devices with reduced packaging size, enhancing storage capabilities in compact formats such as USB flash drives and mobile phones.
Implementation Method 1
uses inversion bit lines in order to eliminate the need for implanted bit lines
Implementation Method 2
polysilicon regions to create inversion bit lines that conduct source and drain voltages
Data Source
AI summary
A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based memory device that uses inversion bit lines is disclosed.