3D NAND Bit Line IR Drop Compensation for In-Memory Compute
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Solution Overview
Problem
Existing 3D NAND memory systems face challenges in performing multiply and accumulate (MAC) and vector-matrix multiplication (VMM) operations efficiently due to bit line IR drop, which affects computing accuracy, precision, and performance by reducing memory cell current and introducing non-ideal effects such as drain-induced barrier lowering (DIBL).
Innovation Solution
A 3D NAND memory system compensates for bit line IR drop by calculating corrected target states for each NAND memory cell to improve accuracy and precision, using correction factors to adjust voltages at the drain ends of NAND strings, thereby enhancing the performance of in-memory compute operations like VMM and MAC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If in-memory compute operations are performed in 3D NAND memory systems, then computing performance and energy efficiency are improved, but bit line IR drop causes reduced computing accuracy and precision
Solution Approach 1:
The system performs preliminary actions by calculating corrected target states for each NAND memory cell before programming. Correction factors are determined based on bit line characteristics and used to adjust the programming process, compensating for IR drop effects before they degrade computing accuracy.
Solution Approach 2:
The system changes physical parameters by adjusting voltages at the drain ends of NAND strings using correction factors. This voltage adjustment compensates for the IR drop along bit lines, ensuring that memory cells are programmed to accurate target states despite the resistance-induced voltage loss.
2Speed
If higher currents are used to improve computing speed, then processing time is reduced, but bit line IR drop increases causing greater voltage loss and reduced accuracy
Solution Approach 1:
The system dynamically adjusts voltage parameters by applying correction factors to the drain end voltages of NAND strings. This compensation mechanism allows higher programming currents to be used for faster processing while maintaining voltage accuracy through real-time parameter adjustment.
Solution Approach 2:
The system implements feedback by calculating correction factors based on bit line characteristics and using these factors to adjust programming voltages. This closed-loop approach ensures that voltage accuracy is maintained even when programming currents vary to optimize processing speed.
3Productivity
If more NAND strings are connected to each bit line to increase parallelism, then throughput is improved, but IR drop effects are amplified due to cumulative resistance
Solution Approach 1:
The system applies local quality by calculating and applying individual correction factors for each NAND memory cell based on its specific position and the characteristics of its associated bit line segment. This localized compensation approach addresses IR drop variations across different parts of the memory array, maintaining current precision even with high parallelism.
4Measurement precision
If bit line resistance is reduced to minimize IR drop, then voltage accuracy is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The system introduces an intermediary computational step by calculating correction factors that model the IR drop effects. Rather than physically modifying the bit lines to reduce resistance, the correction factors act as a software/firmware intermediary that compensates for the electrical characteristics, achieving voltage precision without increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates the impact of bit line IR drop, improving the accuracy, precision, and performance of in-memory computing by compensating for voltage dependencies at the NAND memory cell current, thus optimizing the computing process.
Implementation Method 1
bit line IR drop by calculating corrected target states for each NAND memory cell
Implementation Method 2
introducing non-ideal effects such as drain-induced barrier lowering (DIBL)
Data Source
AI summary
Technology for NAND in-memory compute. A memory system accesses a target state for each NAND memory cell in a computation unit to represent a numerical value. The NAND memory cells in the computation unit reside and one or more NAND strings associated with a corresponding one or more bit lines. The target state may be, for example, a target threshold voltage or a target current. The memory system calculates a corrected target state for each NAND memory cell in the computation unit to compensate for IR drop along the one or more bit lines. The memory system programs each NAND memory cell in the computation unit to the corresponding corrected target state.