NAND Memory Array Multi-Bit Storage PHINES Architecture
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Solution Overview
Problem
Conventional NAND type flash memory arrays are limited to one bit per cell operation, require complex fabrication processes due to double polysilicon and metal layers, and have precise bit line contact requirements, making them unsuitable for multi-bit per cell applications.
Innovation Solution
A NAND type multi-bit charge storage memory array is developed, featuring memory strings with select transistors connected in series, shared and individual bit lines, and using hot-hole injection nitride electron storage (PHINES) cells, which allows for 2 bits per cell operation and simplifies the fabrication process by reducing the number of polysilicon and metal layers needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional NAND floating gate memory array is used, then one bit per cell operation is achieved, but multi-bit per cell operation capability is lost
Solution Approach 1:
The patent changes the fundamental parameter of charge storage mechanism from conventional floating gate to charge storage well structure, enabling multi-bit storage per cell by creating multiple distinct charge storage regions within each memory cell. This parameter change allows the same physical cell to store multiple bits of information through different charge distribution patterns, thereby achieving multi-bit per cell operation without proportionally increasing device complexity
Solution Approach 2:
The memory cell structure is segmented into multiple charge storage regions (first charge storage region and second charge storage region) within a single cell. Each region can independently store charge representing different bit values, allowing the cell to function as multiple storage units. This segmentation enables multi-bit storage capability while maintaining a relatively simple overall cell structure compared to using multiple separate cells
2Ease of manufacture
If conventional NAND floating gate memory array is used, then double polysilicon layers and double metal layers are required, but fabrication process is simplified
Solution Approach 1:
The patent extracts and eliminates the need for double polysilicon layers and double metal layers from the conventional memory array structure. By redesigning the charge storage mechanism to use charge storage wells formed in the substrate or device isolation regions, the invention removes the requirement for multiple polysilicon gating layers and corresponding metal interconnect layers, thereby simplifying the fabrication process and reducing manufacturing complexity
Solution Approach 2:
The patent uses device isolation regions or substrate regions as charge storage wells, effectively repurposing existing structural elements that would otherwise be non-functional or waste material. This approach eliminates the need for additional expensive polysilicon and metal layers, reducing both material costs and fabrication complexity while achieving the desired multi-bit storage functionality
3Manufacturing precision
If conventional NAND floating gate memory array is used, then bit line contact process is precise, but manufacturing difficulty increases
Solution Approach 1:
The patent changes the spatial arrangement of bit line contacts by utilizing the vertical dimension and device isolation regions. Instead of requiring precise lateral alignment of contacts with small pitch between bit lines, the invention positions charge storage regions in the vertical dimension within isolation regions, allowing bit line contacts to be formed at larger pitch with reduced precision requirements while still achieving proper electrical connection to the memory cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new memory array architecture enables efficient multi-bit per cell operation with reduced select transistor overhead and simplified fabrication, lowering production costs and easing the bit line contact process, while maintaining a lower contact pitch between bit lines.
Implementation Method 1
each of which includes one or more charge storage memory cells... The charge storage memory cells are programmed by hot-hole injection nitride electron storage (PHINES) cells
Implementation Method 2
The charge storage memory cells are programmed by hot-hole injection nitride electron storage (PHINES) cells
Data Source
AI summary
A NAND type multi-bit charge storage memory array comprises a first and a second memory strings each of which includes one or more charge storage memory cells and two select transistors. The charge storage memory cells are connected in series to form a memory cell string. The two select transistors are connected in series to both ends of the memory cell string, respectively. The NAND type multi-bit charge storage memory array further comprises a shared bit line and a first and a second bit lines. The shared bit line is connected with the first ends of the first and the second memory strings. The first and the second bit lines are connected to the second ends of the first and the second memory strings, respectively. The first select transistor and the second select transistor of each memory string are controlled by a first and a second select transistor control lines, respectively.