3D NAND Memory Block Short-Circuited Back Gate and Dummy Word Line
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Solution Overview
Problem
The challenge in 3D semiconductor memory devices is the larger size of memory blocks, which complicates interchangeability with planar semiconductor memory devices, requiring a system design change and necessitating a reduction in block size to maintain compatibility.
Innovation Solution
The nonvolatile semiconductor memory device incorporates a structure with a memory string comprising memory cells, dummy transistors, and a back gate transistor connected in series, with the back gate line and dummy word line being short-circuited, allowing for a smaller memory block configuration by reducing the number of upper wiring layers needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory blocks are arranged in a conventional 3D structure with separate back gate lines and dummy word lines, then the memory block can provide necessary electrical functions, but the memory block size becomes large and requires more upper wiring layers
Solution Approach 1:
The patent merges the back gate line and dummy word line into a single conductive layer by short-circuiting them at specific positions. This consolidation reduces the number of separate wiring layers needed in the 3D memory structure, thereby decreasing the overall memory block size and simplifying the device architecture while maintaining necessary electrical functions.
Solution Approach 2:
The conductive layer is designed to serve multiple functions simultaneously: it acts as both the back gate line for controlling the back gate transistor and the dummy word line for selecting memory cells. This multi-functionality eliminates the need for separate dedicated wiring layers for each function, reducing complexity and space requirements.
2Adaptability or versatility
If the memory block size is reduced to improve compatibility with planar semiconductor memory devices, then interchangeability is maintained, but the electrical functions of back gate control and word line selection may be compromised
Solution Approach 1:
By combining the back gate line and dummy word line into a single conductive layer with strategic short-circuit connections, the patent achieves compact memory block dimensions compatible with planar devices while preserving the electrical integrity of both back gate control and word line selection functions.
Solution Approach 2:
The conductive layer is segmented into different functional regions: portions that serve as back gate line connections and portions that serve as dummy word line connections. The short-circuit positions are strategically placed to enable proper electrical isolation and connection for each function, ensuring reliable operation despite the reduced block size.
Data Source
AI summary
A nonvolatile semiconductor memory device according to one aspect includes a semiconductor substrate, a memory string, a plurality of first conductive layers, a second conductive layer, and a third conductive layer. The memory string has a plurality of memory cells, a dummy transistor and a back gate transistor connected in series in a direction perpendicular to the semiconductor substrate. The plurality of first conductive layers are electrically connected to gates of the memory cells. The second conductive layer is electrically connected to a gate of the dummy transistor. The third conductive layer is electrically connected to a gate of the back gate transistor. The second conductive layer is short-circuited with the third conductive layer.