NAND Memory Read-Voltage Correction Across Stacked Layers
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Solution Overview
Problem
Existing NAND-type flash memory systems face challenges in efficiently managing and correcting read voltage shifts across multiple layers in three-dimensionally stacked memory cells, leading to data integrity issues.
Innovation Solution
A memory system with a memory controller that includes a storage circuit to manage correction value tables for read voltages in each layer, allowing for optimized shift amounts and updates based on decoded data, thereby improving data accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If correction value tables are maintained for each layer in three-dimensionally stacked memory cells, then data integrity is improved, but device complexity increases
Solution Approach 1:
The correction value table is segmented into multiple layers, with each layer having its own correction value table. This allows independent management of read voltage shifts for each memory layer, improving data integrity without requiring a single complex centralized table. The segmentation enables targeted corrections specific to each layer's characteristics.
Solution Approach 2:
The patent extends the correction value table structure from a single-dimension approach to a multi-dimensional structure that accounts for layer depth in three-dimensionally stacked memory cells. By adding the layer dimension, the system can independently manage read voltage shifts across multiple stacked layers, resolving the complexity issue through structured organization rather than unstructured complexity.
2Measurement precision
If read voltages are dynamically adjusted across stacked memory layers, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The read voltage is made dynamic rather than fixed, allowing adjustment based on detected shifts in each memory layer. The system continuously monitors and adjusts read voltages across stacked layers, improving measurement precision while managing complexity through automated dynamic adaptation rather than static complex configurations.
Solution Approach 2:
The system implements feedback mechanisms where read voltage shifts are detected and correction values are updated based on actual performance. This feedback loop enables precise voltage adjustment across memory layers while simplifying the overall system through self-correction rather than requiring complex pre-configured voltage management.
3Reliability
If correction value tables are updated based on decoded data, then data integrity is improved, but loss of time occurs during update operations
Solution Approach 1:
Correction value tables are updated in advance during idle periods or between operations, rather than waiting for errors to occur. This preliminary action ensures that correction data is ready when needed, minimizing impact on operational time while maintaining high data integrity through proactive table maintenance.
Solution Approach 2:
The system performs periodic updates of correction value tables at scheduled intervals rather than continuously or on-demand. This periodic approach balances data integrity improvements with time loss by updating tables at optimal moments without disrupting normal read/write operations, achieving a rhythm that maintains reliability while minimizing operational impact.
Data Source
AI summary
A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.