NAND Memory Assembly Rings That Protect Conductive Posts During Etching
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Solution Overview
Problem
There is a need for improved methods of forming integrated memory devices, particularly NAND memory devices, to enhance the manufacturing process and improve the performance of memory cells.
Innovation Solution
The use of protective material in the form of annular rings or laminates is incorporated around lower regions of conductive posts during etching processes to protect these structures and enhance the integrity of the integrated assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching processes are performed on the integrated assembly, then memory cells and conductive structures are formed, but conductive posts may be damaged or compromised during the etching process
Solution Approach 1:
A sacrificial material is introduced as an intermediary protective layer around the conductive posts during etching processes. This sacrificial material acts as a mediator that shields the conductive posts from direct exposure to etchants, preventing damage while allowing the etching process to proceed to form the desired memory cell structures. The sacrificial material is subsequently removed after serving its protective function.
2Reliability
If protective material is added around conductive posts, then conductive post integrity is improved, but device complexity increases
Solution Approach 1:
The sacrificial material is applied in advance to the conductive posts before the etching process begins. This preliminary protective action ensures that the conductive posts are shielded from damage during subsequent manufacturing steps. By performing the protection step beforehand, the process integrates smoothly into the existing manufacturing flow without requiring complex real-time adjustments or additional monitoring systems.
Data Source
AI summary
Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.