NAND Memory Charge-Blocking Segments for Data Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NAND memory architectures face data retention issues due to charge migration between memory cells caused by charge-trapping material extending across multiple cells, leading to inefficiencies in charge storage and retrieval.
Innovation Solution
Incorporating breaks in the charge-trapping material between memory cells and employing a vertical stack configuration with alternating insulative and conductive levels, including high-k dielectric materials and charge-blocking layers to impede charge migration and enhance data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge-trapping material is used to store charge in NAND memory cells, then charge storage capability is improved, but charge migration between adjacent memory cells occurs causing data retention issues
Solution Approach 1:
The charge-blocking material is divided into multiple vertically-spaced segments rather than forming a continuous layer. These segmented blocks are positioned at different vertical levels to interrupt charge migration pathways while preserving charge storage in the charge-trapping material layers between segments.
Solution Approach 2:
Charge-blocking material segments are introduced as intermediary structures between adjacent memory cells. These segments act as barriers that mediate the interaction between neighboring cells, preventing charge migration while allowing each cell to maintain its charge storage functionality.
2Reliability
If charge-blocking material is introduced to prevent charge migration, then data retention is improved, but device structure becomes more complex
Solution Approach 1:
The charge-blocking material is divided into multiple vertically-spaced segments rather than forming a continuous layer. These segmented blocks are positioned at different vertical levels to interrupt charge migration pathways while preserving charge storage in the charge-trapping material layers between segments.
Solution Approach 2:
The solution introduces vertical segmentation of charge-blocking material at different height levels within the memory stack. By utilizing the vertical dimension strategically, the patent creates multiple barriers against charge migration without requiring additional lateral space or complex planar structures.
3Reliability
If vertical stack configuration with alternating insulative and conductive levels is implemented, then charge migration is reduced, but manufacturing process complexity increases
Solution Approach 1:
The charge-blocking material is divided into multiple vertically-spaced segments rather than forming a continuous layer. These segmented blocks are positioned at different vertical levels to interrupt charge migration pathways while preserving charge storage in the charge-trapping material layers between segments.
Solution Approach 2:
The memory structure employs periodic alternating layers of insulative and conductive materials in a vertical stack configuration. This periodic arrangement creates regular intervals for charge blocking and storage functions, enabling systematic manufacturing through repeated deposition cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces charge migration, improving data retention and string current performance by creating vertically-spaced segments of charge-blocking and charge-storage materials, thereby enhancing the reliability and efficiency of NAND memory cells.
Implementation Method 1
high-k dielectric materials
Implementation Method 2
charge-blocking layers to impede charge migration
Data Source
AI summary
Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.


