NAND Memory Read Voltage Prediction for Aging Data Reliability
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Solution Overview
Problem
The accuracy of reading data stored in NAND memory cells deteriorates over time due to changes in stored charge, affecting data retention and reliability.
Innovation Solution
A memory device and system that utilize a peripheral circuit to obtain a target valley voltage in a first stage and a predicted valley voltage in a second stage, with read voltages in the second stage being lower than in the first stage, to improve data reading accuracy by adjusting read operations based on these voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read operations are performed using fixed read voltages in NAND memory cells, then the reading process is simple and fast, but the accuracy of reading data deteriorates over time due to charge storage changes
Solution Approach 1:
The patent applies preliminary action by obtaining target valley voltage in a first stage and predicted valley voltage in a second stage before performing the actual read operation. The peripheral circuit pre-calculates the appropriate read voltage based on the predicted valley voltage, which compensates for charge storage changes in memory cells. This preliminary voltage adjustment ensures accurate reading even as memory cells degrade over time, without requiring complex real-time adjustments during the read operation itself.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the read voltage parameter based on the predicted valley voltage. Instead of using fixed read voltages, the system modifies the read voltage parameter according to the actual charge storage state of the memory cells. The peripheral circuit changes the read voltage parameter to match the target valley voltage, which compensates for degradation effects and maintains reading accuracy throughout the memory device's operational life.
2Reliability
If the read voltage is reduced in subsequent stages to compensate for charge changes, then reading accuracy is maintained, but the voltage management becomes more complex
Solution Approach 1:
The patent applies feedback by using the target valley voltage obtained in the first stage to inform and adjust the read voltage in subsequent stages. The peripheral circuit continuously monitors the charge storage state through the valley voltage measurement and uses this feedback information to adjust the read voltage parameter. This feedback mechanism ensures that the read voltage remains appropriate even as charge storage changes over time, maintaining reliability without requiring complex manual voltage management.
Solution Approach 2:
The patent implements universality by designing the peripheral circuit to handle multiple voltage management functions through a single integrated mechanism. The same peripheral circuit that obtains the target valley voltage also generates the predicted valley voltage and adjusts the read voltage accordingly. This multi-functional approach consolidates voltage management tasks, reducing the overall system complexity while maintaining the ability to adapt read voltages for reliable data retention across different stages and conditions.
Data Source
AI summary
Examples of the present disclosure disclose a memory device, a memory system, a memory controller and an operating method, the memory device includes: a preset number of the memory cells form one code word, and the multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple stages, the multiple stages include a first stage and a second stage, and the read voltage corresponding to the second stage is less than the read voltage in the first stage; peripheral circuit coupled to the array of memory cells and configured to: obtain the target valley voltage in the first target stage; take the target valley voltage as a read voltage at which a read operation is performed on the at least one code word; and obtain the predicted valley voltage in the second target stage in accordance with the target valley voltage in the first target stage.