NAND Memory Read-Voltage Tuning for Target Valley Detection

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Solution Overview

Problem

As the use time increases, charges stored in NAND memory cells vary due to repeated read operations and cross temperature, affecting the correctness of data reading.

Innovation Solution

A memory device and system that adjusts the read voltage to determine a target valley voltage by iteratively refining it based on a first result and threshold conditions, using mapping functions and correction coefficients to ensure accurate data reading.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If read voltage is adjusted iteratively to determine target valley voltage, then data reading accuracy is improved, but device complexity and operation time increase

Engineering Contradiction:
Improvedata reading accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the read voltage adjustment process into distinct stages: initial read voltage application, first result acquisition, threshold determination, voltage adjustment, and target valley voltage determination. Each stage processes specific parameters independently, reducing overall system complexity while maintaining accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-determining thresholds and adjustment parameters before the main read operation. The first threshold and correction coefficients are calculated in advance based on predicted valley voltages, allowing the actual read operation to proceed more efficiently with reduced real-time computation requirements.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If iterative voltage adjustment is performed to determine target valley voltage, then data reading accuracy is improved, but operation time increases

Engineering Contradiction:
Improvedata reading accuracyVSAvoidoperation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent implements feedback mechanisms where the first result from initial reads is used to determine the first threshold, which then guides the voltage adjustment process. This feedback loop allows the system to converge to the target valley voltage efficiently by continuously refining the read voltage based on previous measurement outcomes.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes key parameters during the process: read voltage is adjusted based on the difference between first result and first threshold, and correction coefficients are applied to refine the target valley voltage determination. These parameter changes enable adaptive optimization of read accuracy without requiring excessive iterative steps.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If more processing is done in memory device rather than memory controller, then transmission time is reduced, but device complexity increases

Engineering Contradiction:
Improvetransmission timeVSAvoiddevice complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent enables the memory device to perform self-service operations by determining its own target valley voltage using internal processing of read results and threshold comparisons. This self-determination capability eliminates the need for extensive communication with the memory controller, reducing transmission time while distributing computational workload to where the data resides.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250266101A1Memory device, memory system, memory controller, and operation method
Publication Date: 2025.08.21 YANGTZE MEMORY TECH CO LTD
  • US20250266101A1 patent drawing
  • US20250266101A1 patent drawing
  • US20250266101A1 patent drawing

AI summary

Examples of the present application provide a memory device, a memory system, a memory controller, and an operation method. The memory device includes: an array of memory cells comprising multiple memory cells, wherein a preset number of memory cells form one codeword; and a peripheral circuit coupled with the array of memory cells and configured to: obtain a first result corresponding to at least one codeword at a target read voltage; obtain a first threshold according to the corresponding first result at the target read voltage; make at least one adjustment to the target read voltage, and after each adjustment, obtain a corresponding first result at the adjusted target read voltage; and determine a target valley voltage.