NAND Memory Multi-Plane Read Architecture for Asynchronous Access

The patent divides the control function into multiple independent read units (first read unit, second read unit, third read unit, etc.), each capable of independently controlling read operations on different memory planes. This segmentation allows parallel read operations across multiple planes simultaneously, improving system performance while maintaining manageable control complexity through modular design.

The patent implements dynamic control where each read unit can independently initiate and manage read operations on its assigned memory plane without waiting for other planes to complete. This dynamic operation mode allows the system to adapt to different read requirements and issue read instructions flexibly, even when the memory device is busy with other operations, thereby improving operation flexibility.

The patent segments the read control function into multiple dedicated read units, where each unit is responsible for controlling read operations on specific memory planes. This segmentation enables parallel read operations that improve speed while keeping each control unit relatively simple in structure, thus balancing speed improvement with acceptable device complexity.

The patent introduces a multiplexing circuit as an intermediary component that manages control signals between the multiple read units and the memory planes. The multiplexing circuit receives control signals from different read units and routes them to the appropriate memory planes, simplifying signal management while enabling flexible asynchronous read operations across multiple planes simultaneously.