NAND Page Buffer Segmentation Isolates Coupling Lines
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Solution Overview
Problem
The presence of a common node in page buffers for NAND flash memories can cause issues during data transfer due to voltage leakage and unpredictable voltage variations, leading to incorrect operation and significant electrical power wastage.
Innovation Solution
The implementation of a page buffer that avoids the use of a common line for data transfer by employing programming state change enabling means, reading, receiving, combining, and conditioning mechanisms to manage the coupling line, ensuring isolation during the combining phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a common node is used for data transfer in page buffer, then data transfer capability is provided, but voltage leakage and unpredictable voltage variations occur leading to incorrect operation and significant electrical power wastage
Solution Approach 1:
The patent divides the data transfer path into separate dedicated lines for each memory cell column, eliminating the common node. Each column has its own isolated coupling line that connects the page buffer to the memory cell, preventing voltage leakage and unpredictable variations that occur when multiple columns share a common node.
Solution Approach 2:
The patent introduces isolation mechanisms (isolation transistors and isolation circuits) as intermediaries between the page buffer and memory cells. These intermediaries control the coupling and decoupling of signals, ensuring that voltage variations in one column do not affect other columns, thereby eliminating the harmful effects of the common node while maintaining data transfer capability.
2Ease of operation
If a common node is used for data transfer in page buffer, then data transfer capability is provided, but significant electrical power is wasted due to voltage leakage and unpredictable variations
Solution Approach 1:
The patent segments the power consumption sources by providing separate dedicated coupling lines for each column. This eliminates the cumulative power waste that occurs in a common node configuration where voltage leakage from multiple columns adds up, thereby significantly reducing overall electrical power consumption while maintaining data transfer functionality.
3Reliability
If isolation during combining phase is implemented, then reliability and efficiency of data transfer are enhanced, but device complexity increases due to additional isolation mechanisms
Solution Approach 1:
The patent combines the isolation function with the existing data transfer infrastructure by integrating isolation transistors into the coupling line architecture. Rather than adding completely separate isolation systems, the isolation mechanisms are merged with the data path, allowing reliable isolated data transfer while minimizing the increase in device complexity.
Data Source
AI summary
A page buffer for an electrically programmable memory is provided. The page buffer includes a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, wherein the data bits include at least a first data bits group and a second data bits group and at least one read/program unit having a coupling line operatively associable with selected memory cells.