3D NAND Memory Pillar Layout for Uniform Bit Line Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In three-dimensional NAND flash memory structures, variations in parasitic capacitance between bit lines due to uneven distribution of memory pillars lead to inconsistent data read times, and the alignment of these pillars can cause increased production complexity.
Innovation Solution
The memory pillars in adjacent blocks are arranged with a directional deviation, leveling the parasitic capacitance across bit lines by adjusting their layout to minimize variations in data read times and reduce production complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory pillars are aligned in a regular grid pattern, then manufacturing process is simpler, but parasitic capacitance varies between bit lines causing inconsistent data read times
Solution Approach 1:
The patent applies asymmetry by intentionally deviating the arrangement of memory pillars from a regular grid pattern. Specifically, pillars in alternate blocks are shifted by half a pitch in the first direction, creating an asymmetric layout that equalizes parasitic capacitance values across all bit lines, thereby ensuring consistent data read times while maintaining manufacturability.
Solution Approach 2:
The patent implements local quality by applying different pillar arrangement patterns to different blocks of memory. Blocks adjacent to bit line groups are arranged with a half-pitch deviation, while other blocks maintain standard alignment. This localized variation optimizes parasitic capacitance distribution specifically at critical interfaces without compromising overall manufacturing simplicity.
2Reliability
If memory pillars are arranged with deviation to equalize parasitic capacitance, then data read time consistency improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory array into multiple blocks, each with specific pillar arrangement patterns. By segmenting the structure and applying deviation only to specific blocks adjacent to bit line groups, the patent achieves parasitic capacitance equalization locally where it matters most, while keeping other blocks simpler for manufacturing.
Solution Approach 2:
The patent applies partial action by implementing pillar deviation only in specific blocks rather than uniformly across the entire array. This selective application achieves the necessary parasitic capacitance equalization at critical interfaces without unnecessarily complicating the manufacturing process for the entire memory device.
Data Source
AI summary
According to one embodiment, a memory device includes: a plurality of first conductive layers aligned apart from each other in a first direction; a first member extending in a second direction intersecting the first direction and dividing the first conductive layers into a first portion and a second portion aligned in a third direction intersecting the first direction and the second direction; a plurality of first memory pillars each extending in the first direction and intersecting with each of the first portions of the first conductive layers; and a plurality of second memory pillars each extending in the first direction and intersecting with each of the second portions of the first conductive layers. The second memory pillars are disposed to be deviated with respect to the first memory pillars in the second direction as viewed in the first direction.