NAND Memory Power Loss Detection via Read Level Calibration
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Solution Overview
Problem
Flash memory devices face challenges in distinguishing between asynchronous power loss (APL) and margin loss, leading to inefficiencies and unnecessary data loss, as both can result in bit errors and affect the reliability of data storage in NAND flash memory cells.
Innovation Solution
The implementation of methods to differentiate between APL-affected and margin loss-affected physical pages by analyzing the effects on threshold voltage distributions, using read level calibration and comparison of read level differences to determine the type of loss, allowing for appropriate recovery or discard actions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory error handling is used without distinguishing between APL and margin loss, then all affected pages are discarded conservatively, but this leads to unnecessary data loss and resource waste
Solution Approach 1:
The patent segments the error handling process by dividing affected pages into two distinct categories: APL-affected pages and margin loss-affected pages. This segmentation is achieved through analyzing threshold voltage distributions and comparing read level differences, allowing each type of affected page to be handled differently - APL pages are discarded while margin loss pages are recovered through re-programming, thus preventing unnecessary data loss while maintaining reliability
Solution Approach 2:
The patent utilizes parameter changes in threshold voltage distributions to distinguish between APL and margin loss. By monitoring shifts in threshold voltage characteristics and read level differences, the system can identify the specific type of degradation affecting each page, enabling differentiated recovery strategies that optimize both reliability and data retention
2Reliability
If all pages with bit errors are discarded to ensure data integrity, then data reliability is maintained, but processing efficiency and resource utilization decrease
Solution Approach 1:
The patent segments the error handling process by dividing affected pages into two distinct categories: APL-affected pages and margin loss-affected pages. This segmentation is achieved through analyzing threshold voltage distributions and comparing read level differences, allowing each type of affected page to be handled differently - APL pages are discarded while margin loss pages are recovered through re-programming, thus preventing unnecessary data loss while maintaining reliability
Solution Approach 2:
The patent implements a selective discard and recover strategy where APL-affected pages are discarded to maintain data integrity, while margin loss-affected pages are recovered through re-programming operations. This approach significantly improves processing efficiency by retaining usable data that would otherwise be discarded, while still ensuring that genuinely corrupted APL pages are removed from service
3Measurement precision
If read level calibration and threshold voltage analysis are performed to distinguish APL from margin loss, then accurate identification of affected pages is achieved, but device complexity and measurement requirements increase
Solution Approach 1:
The patent implements self-service mechanisms where the memory device performs its own diagnostics and classification of affected pages using built-in threshold voltage distribution analysis and read level calibration capabilities. The device autonomously identifies whether pages are APL-affected or suffering from margin loss through internal measurements, reducing the need for external testing equipment and simplifying the overall measurement complexity while maintaining high identification accuracy
Data Source
AI summary
Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first physical page of a number of physical pages from an initial first read level position to a calibrated first read level position. The first read level may be between a first threshold voltage distribution corresponding to a first logical state of the at least four logical states and a second threshold voltage distribution corresponding to a second logical state of the at least four logical states. Also, the first threshold voltage distribution may be a highest threshold voltage distribution for the first physical page. The memory controller may calibrate a second read level for the first physical page that is lower than the first read level from an initial second read level position to a calibrated first read level position. The memory controller may determine to refresh at least one logical page stored at the first physical page based at least in part on a first read level difference between the initial first read level and the calibrated first read level and a second read level difference between the initial second read level and the calibrated second read level.