3D NAND Memory Read Characteristics via Charge Region Segmentation
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Solution Overview
Problem
Current three-dimensional NAND flash memory devices face challenges in enhancing read characteristics, particularly due to the sharp subthreshold slope of transistors in memory cells, which affects the performance and accuracy of data reading.
Innovation Solution
The semiconductor memory device incorporates a positive feedback type structure with n and p-type semiconductor regions, stacked conductive layers, and charge storage regions, where a control circuit manages voltages to prevent charge storage in specific regions, enabling enhanced read characteristics by controlling the charge amount in each memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a positive feedback type three-dimensional NAND flash memory is used to enhance read characteristic, then the read characteristic is improved, but the device complexity increases due to additional p-type semiconductor region and control circuit requirements
Solution Approach 1:
The memory device is divided into multiple charge storage regions (first charge storage region and second charge storage region) within each memory cell, allowing independent control of charges in different regions. This segmentation enables the positive feedback mechanism to operate on specific regions while keeping other regions stable, thereby improving read characteristic without requiring complete redesign of the entire memory structure.
Solution Approach 2:
The patent applies different impurity concentrations to different regions: the first charge storage region has a first conductive impurity concentration, the second charge storage region has a second conductive impurity concentration, and the semiconductor layer has an impurity concentration lower than both. This local differentiation of electrical properties enables selective charge control in different regions, achieving enhanced read characteristic through localized positive feedback while maintaining overall device functionality.
2Quantity of substance
If charge storage regions are increased to improve memory capacity, then the integration density is improved, but the difficulty of controlling charge distribution increases
Solution Approach 1:
Each memory cell contains multiple charge storage regions (first and second charge storage regions) that can independently store charges. This segmentation allows the memory device to increase storage capacity by utilizing multiple charge storage zones per cell while maintaining independent control over each region's charge state through selective voltage application to adjacent conductive layers.
Solution Approach 2:
The patent controls charge distribution by changing electrical parameters (voltage and impurity concentration) in different regions. By applying different voltages to adjacent conductive layers and utilizing regions with different impurity concentrations, the system can precisely control where charges are stored and how they are distributed, making multi-region charge control manageable despite increased capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the read characteristic of three-dimensional NAND flash memory devices by preventing charge storage in designated regions, reducing erroneous readings and enhancing data reading speed, thus optimizing the performance of the memory device.
Implementation Method 1
a control circuit that controls a voltage applied to the n conductive layers so as to prevent charges from being stored in at least one of the n charge storage regions
Data Source
AI summary
An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.