3D NAND Stack Layout with Insulating Patterns for Data Retention
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Solution Overview
Problem
Three-dimensional non-volatile memory devices face challenges in increasing integration density and operational reliability due to limitations in the stacking of memory cells over a substrate, leading to interference and reduced data retention characteristics.
Innovation Solution
A semiconductor device with a stacked structure of insulating and conductive layers, a hard mask pattern, and insulating patterns that protrude further towards the channel structure than the conductive layers, along with a memory layer filling the spaces between the insulating patterns, which mitigates charge movement and improves data retention by reducing interference between memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are stacked in a vertical direction over a substrate to increase integration density, then integration density is improved, but interference between memory cells increases and data retention characteristics deteriorate
Solution Approach 1:
The patent divides the vertical stack into multiple memory cell layers separated by insulating layers and channel layers. Each memory cell is segmented into distinct components (gate electrode, insulating layer, channel layer, memory layer) arranged in repeating units, which isolates charge storage regions and reduces inter-cell interference while maintaining high integration density through vertical stacking
Solution Approach 2:
The patent introduces insulating layers as intermediary elements between adjacent memory cells and gate electrodes. These insulating layers act as mediators that electrically isolate charge storage regions, preventing charge leakage and interference between neighboring memory cells, thereby improving data retention characteristics while enabling continued vertical scaling
2Productivity
If memory cells are stacked vertically to increase integration density, then integration density is improved, but interference between memory cells increases
Solution Approach 1:
The patent divides the vertical stack into multiple memory cell layers separated by insulating layers and channel layers. Each memory cell is segmented into distinct components (gate electrode, insulating layer, channel layer, memory layer) arranged in repeating units, which isolates charge storage regions and reduces inter-cell interference while maintaining high integration density through vertical stacking
Solution Approach 2:
The patent introduces insulating layers as intermediary elements between adjacent memory cells and gate electrodes. These insulating layers act as mediators that electrically isolate charge storage regions, preventing charge leakage and interference between neighboring memory cells, thereby improving data retention characteristics while enabling continued vertical scaling
Data Source
AI summary
A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern located on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns, wherein a sidewall of each of the conductive layers protrudes farther towards the channel structure than a sidewall of the hard mask pattern, and wherein the insulating patterns protrude farther towards the channel structure than the sidewall of each of the conductive layers.