NAND String Module Buffer for High-Density Memory Read Speed
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Solution Overview
Problem
Existing flash memories, such as NAND-type flash memories, face challenges in scalability to Giga-bit densities without a substantial loss of performance, particularly in achieving high-speed and high-density capabilities.
Innovation Solution
The proposed memory device incorporates a sense amplifier module with a pre-charge module and differential amplifier configuration, utilizing N-type field effect transistors and capacitors to detect the conductive or non-conductive state of storage cells, allowing for efficient data reading and writing while maintaining performance across varying densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND-type flash memory is scaled to Giga-bit densities, then storage capacity increases, but performance deteriorates substantially
Solution Approach 1:
The memory array is divided into multiple string modules, each containing multiple NAND strings. This segmentation allows parallel operation of multiple strings during read and write operations, thereby maintaining high speed performance while achieving Giga-bit storage density through increased parallelism rather than单纯 scaling individual string size.
2Quantity of substance
If more NAND strings are connected to share global bit lines, then storage density increases, but signal detection precision deteriorates due to increased capacitance
Solution Approach 1:
A buffer circuit is introduced as an intermediary component between the NAND strings and the sense amplifier. This buffer isolates the high-capacitance global bit lines from the sense amplifier input, preventing the accumulated capacitance from degrading the signal detection precision. The buffer maintains signal integrity by providing a low-impedance drive capability while allowing the sense amplifier to operate with optimized input conditions.
Solution Approach 2:
The buffer circuit changes the electrical parameters of the signal path by providing strong driving capability with low output impedance. This parameter transformation allows the global bit lines to drive many NAND strings (high capacitance load) while the sense amplifier sees a controlled, low-capacitance source, thereby maintaining measurement precision despite increased storage density.
3Power
If buffer circuit is added to drive global bit lines, then signal driving capability improves, but device complexity increases
Solution Approach 1:
The buffer circuit is designed to perform multiple functions: it drives the global bit lines with high current capability, isolates the sense amplifier from bit line capacitance effects, and provides a controlled impedance interface. By consolidating these multiple functions into a single circuit block, the overall device complexity is minimized while achieving strong signal driving capability for high-density memory operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the memory device to maintain high-speed and high-density performance, effectively addressing the scalability issues of existing flash memories by accurately determining the storage state of cells and optimizing data transfer.
Implementation Method 1
detect the conductive or non-conductive state of storage cells
Data Source
AI summary
During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.