3D NAND Memory String Defect Isolation via Selective Transistor Threshold Control
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Solution Overview
Problem
Existing semiconductor memory devices face inefficiencies in managing defective memory cells, particularly in three-dimensional NAND-type flash memories, where defects can render entire blocks unusable, leading to reduced utilization efficiency and reliability.
Innovation Solution
The semiconductor memory device incorporates a method to store bad string information by setting specific threshold voltages in selective transistors and back gate transistors, allowing for the identification and isolation of defective strings at a granular level, thereby preventing the flow of cell current and maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If entire blocks are marked as defective when containing defective memory cells, then reliability is maintained, but utilization efficiency of memory space deteriorates
Solution Approach 1:
The patent segments the memory structure into hierarchical levels: blocks are divided into strings, and strings are divided into individual memory cells. Instead of marking entire blocks as defective, the system identifies and marks only the specific defective strings within blocks. This segmentation allows selective isolation of defective portions while preserving access to healthy memory regions, thereby maintaining reliability while improving utilization efficiency.
2Reliability
If defective strings are isolated at block level, then data integrity is protected, but memory capacity is reduced
Solution Approach 1:
The patent applies local quality by implementing defect management at the string level rather than block level. Each string can be independently marked as defective using bad string markers, allowing the system to preserve local data integrity in healthy strings while maintaining overall memory capacity. This localized approach ensures that only affected areas are isolated, maximizing usable memory space while protecting data integrity.
3Productivity
If granular-level defect management is implemented, then utilization efficiency improves, but device complexity increases
Solution Approach 1:
The patent implements a nested defect management structure where bad block markers and bad string markers operate at different hierarchical levels. Bad string markers are nested within blocks, and bad block markers contain multiple strings. This nested approach allows the system to manage defects at granular string level while reusing existing block-level infrastructure, thereby improving utilization efficiency without proportionally increasing device complexity.
Data Source
AI summary
A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor.