NAND String Erase Control via Ground Select Line Segmentation
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Solution Overview
Problem
Current nonvolatile memory devices require larger erase units, which increases the time for background operations like merge and garbage collection, reducing operation speed and storage capacity utilization.
Innovation Solution
The implementation of a method that includes floating the ground select line of a first string connected to a bit line, applying an erase prohibition voltage to a ground select line of a second string, and applying an erase operation voltage to both strings, allowing for reduced erase unit operations by independently erasing NAND strings connected to a bit line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If larger erase units are used in nonvolatile memory devices, then the storage capacity utilization is improved, but the time for background operations like merge and garbage collection increases, reducing operation speed
Solution Approach 1:
The patent divides the erase operation into finer granules by enabling independent control of different string groups through separate ground select lines. By segmenting the erase unit from traditional large blocks into smaller string-group units, the memory device can perform targeted erase operations on only the necessary portions, reducing the overall time for background operations while maintaining efficient storage capacity utilization
2Productivity
If larger erase units are used in nonvolatile memory devices, then the operation speed is reduced due to longer background operation times, but the device complexity is simplified
Solution Approach 1:
The patent segments the control structure into multiple ground select lines (first ground select line and second ground select line) that can independently control different groups of strings. This segmentation enables fine-grained control over erase operations, allowing the device to optimize operation speed by selectively erasing only the necessary string groups rather than performing blanket erase operations on entire blocks
Solution Approach 2:
The patent implements dynamic control of ground select lines where the first ground select line can be floated (high impedance state) for selected strings during erase operations while the second ground select line receives erase prohibition voltages for unselected strings. This dynamic voltage control mechanism enables flexible adjustment of erase granularity, balancing operation speed requirements with device complexity management
Data Source
AI summary
Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.