3D NAND Program Verify Biasing for Data Retention
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Solution Overview
Problem
Existing memory devices face challenges in maintaining data retention due to the degradation of cell-to-cell interference and word line-to-word line coupling, particularly in three-dimensional NAND memory arrays, which necessitates a shift in the operating window with tier-pitch scaling, but current methods fail to effectively lower the program verify voltage levels below the minimum negative voltage source.
Innovation Solution
The solution involves leveraging word line-to-cell coupling to adjust the program verify voltage levels by using a dedicated, trimmable voltage source or alternative power sources like Vcc or GND to lower the effective program verify voltage levels during the coarse programming pass, specifically for level L1, thereby compensating for interference and improving data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If tier-pitch scaling is implemented to maintain data retention, then memory density is improved, but cell-to-cell interference and word line-to-word line coupling degradation occur
Solution Approach 1:
The patent changes the voltage parameter by applying different voltage levels to adjacent word lines during programming operations. Specifically, it applies a first voltage level to a first set of adjacent word lines and a second voltage level to a second set of adjacent word lines, thereby modifying the electrical parameters to compensate for interference effects caused by tier-pitch scaling and maintain data retention reliability.
2Reliability
If program verify voltage levels are lowered to compensate for interference, then data retention is improved, but the voltage level cannot go below the minimum negative voltage source
Solution Approach 1:
The patent segments the word lines into different sets (first set and second set of adjacent word lines) and applies different voltage levels to each segment. This segmentation allows the system to achieve an effective lower verify level through differential voltage application without requiring a single voltage source to go below the minimum negative voltage limit.
3Reliability
If differential voltage levels are applied to adjacent word lines, then interference compensation is achieved, but device complexity increases
Solution Approach 1:
The patent makes existing voltage sources perform multiple functions by configuring them to provide different voltage levels to different sets of word lines during programming operations. This multi-functionality approach allows interference compensation without adding dedicated voltage sources, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively shifts the program verify voltage levels by 500-700 mV, enhancing data retention and scalability across technology nodes by addressing cell-to-cell and word line-to-word line interference, ensuring reliable operation in three-dimensional NAND memory arrays.
Implementation Method 1
leveraging word line-to-cell coupling to adjust the program verify voltage levels
Data Source
AI summary
A memory device includes an array of memory cells, a plurality of access lines, and a controller. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line is connected to a control gate of a respective memory cell of each string of series-connected memory cells. The controller is configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a first target level. The controller is further configured to apply a first voltage level to a first access line connected to the selected memory cell, and apply a second voltage level higher than the first voltage level to a second access line adjacent to the first access line. The controller is further configured to apply a third voltage level between the first voltage level and the second voltage level to a third access line adjacent to the first access line and connected to an erased memory cell, and sense a first threshold voltage of the selected memory cell.