NAND Flash Word Line Patterning via Sidewall Spacers
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Solution Overview
Problem
Existing methods for forming NAND flash memory arrays face challenges in creating extremely small features and larger features simultaneously without unnecessary process steps, particularly in achieving uniform spacing between word lines and select lines, which can lead to non-uniform etch rates and substrate gouging.
Innovation Solution
The method employs double patterning with sidewall spacers to form word lines with widths smaller than the minimum feature size achievable by direct photolithography, and select lines with edges defined by sidewall spacers, allowing for uniform spacing and efficient formation of both small and larger structures using a common process, including the use of air gap layers and reactive ion etching to define precise dimensions and locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If direct patterning lithography is used to form word lines and select lines, then the process is simple and efficient, but the minimum feature size cannot be achieved for extremely small structures
Solution Approach 1:
The patterning process is divided into two stages: first forming initial structures with direct patterning lithography, then using sidewall spacers to define the final precise dimensions. This segmentation allows each stage to optimize for its specific purpose - the first stage for efficiency and the second for precision - thereby resolving the contradiction between process simplicity and manufacturing precision.
Solution Approach 2:
Initial structures are formed in advance using direct patterning lithography before the sidewall spacer process. These preliminary structures serve as templates that guide the subsequent spacer formation, allowing the final precise dimensions to be achieved through a controlled secondary process rather than requiring the lithography system to achieve the minimum feature size directly.
2Manufacturing precision
If different process methods are used for small features and larger features, then each feature type can be optimized, but the number of process steps increases
Solution Approach 1:
The sidewall spacer process serves as a universal method that can define dimensions for both extremely small word lines and larger select lines. By using the same spacer formation technique for different feature sizes, the process achieves optimized dimension control for all structures without requiring separate specialized processes, thereby maintaining productivity while improving manufacturing precision.
Solution Approach 2:
Sidewall spacers act as an intermediary structure that translates the relatively coarse initial pattern from direct patterning lithography into the final precise dimensions required for both small and large features. This intermediary approach allows a single process flow to achieve optimized dimension control across different feature size ranges without multiplying the number of process steps.
3Adaptability or versatility
If non-uniform spacing is present between word lines and select lines, then the layout flexibility is increased, but etch rate uniformity deteriorates causing over-etching and gouging
Solution Approach 1:
The sidewall spacer process creates uniform spacing intervals between all adjacent lines (both word lines and select lines) by using consistent spacer deposition and etching parameters. This equipotential approach to spacing ensures that the etch process encounters uniform conditions across the entire array, eliminating the non-uniform etch rates and gouging that would result from variable spacing, while still allowing layout flexibility through the initial structure formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of NAND flash memory arrays with uniform spacing between word lines and select lines, preventing over-etching and gouging, thereby improving the uniformity and efficiency of the etching process and reducing the number of process steps required.
Implementation Method 1
forming a plurality of sidewall spacers having a lateral dimension that is less than the minimum resolvable dimension of the photolithographic process
Implementation Method 2
including the use of air gap layers and reactive ion etching to define precise dimensions and locations
Data Source
AI summary
Narrow word lines are formed in a NAND flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines.