NAND Word Line Pre-Boosting Without Channel Pre-Charge
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Solution Overview
Problem
Conventional channel pre-charge in NAND programming consumes significant time and causes high levels of program disturb, particularly in sub-block mode, affecting memory performance and accuracy.
Innovation Solution
Eliminate the channel pre-charge phase by directly discharging the selected word line to a negative word line voltage after program verify, followed by ramping up to bias levels, reducing program disturb and enhancing programming speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional channel pre-charge is used in NAND programming, then programming accuracy is maintained, but programming time increases and program disturb increases
Solution Approach 1:
The patent applies preliminary action by pre-discharging the word line to a negative voltage level before the programming pulse is applied. This pre-discharge prepares the word line by removing excess charge and establishing a lower initial voltage state, which reduces the time needed during the actual programming operation and minimizes program disturb to adjacent cells while maintaining programming accuracy.
Solution Approach 2:
The patent changes the voltage parameter of the word line by introducing a negative word line voltage level that is lower than the typical ground potential. This parameter change allows the word line to be discharged to a more negative state before programming, thereby reducing the voltage swing required during programming and decreasing the time and energy consumption while maintaining cell programming accuracy.
2Manufacturing precision
If conventional channel pre-charge is used in NAND programming, then programming accuracy is maintained, but program disturb increases
Solution Approach 1:
The patent applies preliminary anti-action by pre-discharging the word line to a negative voltage level before programming, which counteracts the harmful effect of program disturb. By establishing this negative voltage state in advance, the patent creates a buffer that reduces the voltage transient and charge injection into adjacent cells during the programming operation, thereby minimizing program disturb while maintaining programming accuracy.
Solution Approach 2:
The patent changes the voltage parameter by introducing a negative word line voltage that is lower than ground potential. This parameter change reduces the voltage swing and current transient during programming, thereby minimizing the harmful electromagnetic interference and charge coupling to adjacent memory cells while preserving the accuracy of the target cell programming.
3Productivity
If channel pre-charge is eliminated, then programming speed increases and program disturb decreases, but word line voltage control complexity increases
Solution Approach 1:
The patent introduces a negative word line voltage as an intermediary voltage level between ground and the programming voltage. This intermediary voltage state serves as a mediator that simplifies the voltage control sequence by providing a stable intermediate step for word line discharge, thereby reducing the overall control complexity despite the addition of a voltage level.
Solution Approach 2:
The patent segments the voltage control process into distinct phases: pre-discharge to negative voltage, hold at negative voltage, and then ramp to programming voltage. This segmentation of the voltage control sequence makes the complex operation more manageable and implementable by breaking it down into simpler, controlled steps.
Data Source
AI summary
To improve programming performance in NAND memory, while maintaining programming accuracy and reducing program disturb, the channel pre-charge phase before a programming pulse can be eliminated. Instead, a read recovery phase after the program verify directly discharges a selected word line from the verify voltage to a negative word line voltage, with non-selected word lines being directly discharged from the read bypass voltage to the negative word line voltage. From the negative word line voltage, the word lines are then ramped up to ground and then on the bias levels of the following programming pulse. These conditions can drive electrons from the charge storage region of the selected memory cell, resulting in a high degree of channel boosting and much less program disturb. Variations of the technique can be applied to NAND memory operable in a sub-block mode where it can be difficult to use the typical channel pre-charge.