NAND Flash Word-Line Pre-Pulse for Faster Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The time overhead and power consumption of verification operations in programming solid-state drive (SSD) memory cells, particularly for multi-level cells of NAND flash, are significant due to the shorter programming pulse time compared to verification operation time, degrading programming performance.
Innovation Solution
A method for programming memory cells that involves applying a predetermined voltage to a selected word line during the pre-pulse phase to reduce capacitive coupling with adjacent unselected word lines, followed by a verification voltage to verify the threshold voltage of the target memory cell, with the predetermined voltage being set close to the target threshold voltage and adjusted for each programming state to expedite the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If verification operations are performed after programming pulses to verify threshold voltage, then programming accuracy is improved, but time overhead and power consumption increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-charging the selected word line to a predetermined voltage (first verification voltage) before the actual verification operation. This preliminary voltage application reduces the voltage change required during verification, thereby reducing verification time while maintaining accuracy. The predetermined voltage is specifically chosen to minimize capacitive coupling effects from adjacent unselected word lines.
Solution Approach 2:
The patent changes the voltage parameter dynamically during the verification process. Instead of using a fixed verification voltage, the system adjusts the voltage applied to the selected word line based on the programming state being verified. Different verification voltages are applied for different target programming states, optimizing the verification process for each state while reducing overall time overhead.
2Reliability
If verification operations are performed with standard voltage application, then verification reliability is maintained, but power consumption increases due to repeated voltage transitions
Solution Approach 1:
The patent reduces power consumption by performing preliminary voltage application to the selected word line before verification. This pre-charging action minimizes the voltage transitions required during the actual verification, thereby reducing energy consumption while maintaining verification reliability through proper voltage control.
Solution Approach 2:
The patent optimizes power consumption by dynamically adjusting verification voltage parameters based on the programming state. Different verification voltages are selected for different target states, allowing the system to use minimal necessary voltage for each verification case, thereby reducing overall power consumption while maintaining reliability.
3Productivity
If programming pulse time is shortened to improve programming speed, then productivity is improved, but verification operations become relatively longer in comparison
Solution Approach 1:
The patent addresses the time overhead by applying a predetermined voltage to the selected word line before the verification operation. This preliminary action prepares the voltage state in advance, reducing the time required for verification and balancing the overall programming cycle time with the shortened programming pulse time.
Solution Approach 2:
The patent optimizes the verification process by changing voltage parameters based on the programming state being verified. This dynamic voltage adjustment allows for faster verification by selecting appropriate verification voltages that minimize the verification time, thereby reducing the relative overhead compared to the shortened programming pulse time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the time required for verification operations by minimizing capacitive coupling effects, thereby enhancing programming performance and efficiency without increasing circuit area or altering the order of programming and verification processes.
Implementation Method 1
reducing voltage changes caused by capacitive coupling between an unselected word line adjacent to the selected word line and the selected word line
Data Source
AI summary
A memory device includes a memory cell array including memory cells, word lines coupled to the memory cells, and peripheral circuits coupled to the word lines. The peripheral circuits are configured to during a pre-pulse phase, apply a first voltage to a first word line of the word lines, during a verification phase after the pre-pulse phase, apply at least one verify voltage to the first word line, and during the pre-pulse phase and the verification phase, apply a pass voltage to a second word line adjacent to the first word line. To apply the first voltage to the first word line, the peripheral circuits are configured to ramp down the first voltage to a first voltage level during a period of applying the pass voltage to the second word line. A voltage level of a first one of the at least one verify voltage is higher than the first voltage level.