Nano-FET Channel Doping Profile for Lower Resistance and Leakage
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges in reducing channel resistance and junction leakage current due to limitations in controlling dopant distribution and electric field management in nanostructure field-effect transistors (nano-FETs).
Innovation Solution
The method involves forming semiconductor nanostructures over a fin with a dummy gate and spacers, using modulated ion implantation with different energies and doses to create a gradient-doped silicon layer, and forming source/drain regions with epitaxial structures to control dopant straggle and reduce electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping methods are used in nano-FETs, then manufacturing process is simple, but channel resistance is high and dopant distribution control is poor
Solution Approach 1:
The doping process is segmented into multiple ion implantation steps with different energies and angles. First, a initial dopant layer is implanted at a first energy level, then a second dopant layer is implanted at a different energy level to create distinct dopant regions with controlled distributions, enabling precise control over channel resistance and electrical characteristics
Solution Approach 2:
The invention changes multiple parameters of the ion implantation process including energy levels, implantation angles, and dopant types across different steps. By varying these parameters systematically, the patent achieves precise control over dopant distribution profiles, creating optimized doping regions that reduce channel resistance while maintaining manufacturing feasibility
2Productivity
If feature size is reduced to increase integration density, then more components fit in given area, but junction leakage current increases
Solution Approach 1:
The invention creates locally optimized doping regions with different dopant concentrations and types in specific areas of the nano-FET. By implementing non-uniform dopant distributions tailored to local requirements, the patent reduces junction leakage current at critical interfaces while maintaining high integration density through continued feature size reduction
Solution Approach 2:
The patent introduces intermediate doping regions that act as transition zones between heavily doped and lightly doped areas. These intermediary regions with graded dopant concentrations serve as mediators that reduce abrupt junctions, thereby minimizing junction leakage current while allowing continued scaling for high integration density
3Productivity
If feature size is reduced to increase integration density, then manufacturing efficiency improves, but channel resistance increases
Solution Approach 1:
The channel region is divided into multiple doping zones through segmented ion implantation steps, each with specific energy and concentration parameters. This segmentation allows optimization of channel resistance by creating regions with appropriate dopant levels throughout the channel, enabling continued feature size reduction without compromising electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced channel resistance and junction leakage current while being compatible with existing manufacturing processes and lowering costs.
Implementation Method 1
A plurality of ion implantation processes are performed on the semiconductor nanostructures to introduce dopants into exposed areas of the semiconductor nanostructures
Data Source
AI summary
A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.