Nano-FET Gate Structure for Uniform Gate Length Etching
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in achieving uniform gate lengths and preventing defects such as silicon germanium residue during the manufacturing of nano-FETs.
Innovation Solution
The use of sacrificial nanosheets with varying germanium concentrations, which are etched differently to compensate for non-uniform etching processes, allows for precise control of gate region profiles and avoids defects by doping with a Group III element like boron.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but achieving uniform gate lengths becomes more difficult
Solution Approach 1:
The gate structure is divided into multiple segments: sacrificial nanosheets with different germanium concentrations are used to define different portions of the gate region. Each nanosheet segment can be independently etched, allowing precise control over the final gate length and improving uniformity despite scaling to smaller features.
Solution Approach 2:
Different regions of the sacrificial nanosheets are doped with different germanium concentrations to create local variations in etch rate. This allows the etching process to self-correct non-uniformities, with faster etching in regions that need material removal and slower etching in regions that need to preserve length, thereby achieving uniform gate lengths across the wafer.
2Productivity
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but defects such as silicon germanium residue increase
Solution Approach 1:
The germanium concentration parameter is varied across different sacrificial nanosheets to optimize etch selectivity and completeness. By adjusting this parameter, the etching process can be tuned to completely remove sacrificial material without leaving silicon germanium residue, even at scaled dimensions, thereby improving device reliability.
Solution Approach 2:
Sacrificial nanosheets are used as temporary, disposable structures that are completely removed after serving their purpose of defining the gate region. Their temporary nature allows for aggressive etching conditions that ensure complete removal without residue, while the nanosheets themselves can be inexpensive to fabricate.
3Speed
If non-uniform etching processes are used, then etching speed may be improved, but gate length uniformity deteriorates
Solution Approach 1:
The germanium concentration in sacrificial nanosheets is specifically engineered to compensate for etching non-uniformity. Regions experiencing slower etching rates are assigned higher germanium concentrations to accelerate local etching, while regions with faster etching use lower concentrations. This parameter modulation maintains overall etching speed while achieving uniform gate lengths.
Solution Approach 2:
The etching process incorporates feedback through the germanium concentration gradient design. The varying germanium content acts as a pre-programmed correction mechanism that responds to local etching conditions, automatically adjusting the etch rate to maintain uniformity without requiring real-time process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in nano-FETs with improved uniformity of gate lengths and reduced defects, enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
etched differently to compensate for non-uniform etching processes
Implementation Method 2
doping with a Group III element like boron
Data Source
AI summary
A device includes a first gate region having a first gate length; a first spacer on a sidewall of the first gate region; a semiconductor layer over the first gate region; a second gate region over the semiconductor layer, wherein the second gate region has a second gate length equal to the first gate length; and a second spacer on a sidewall of second gate region, wherein the second spacer is wider than the first spacer.