Nanodot Memory Cell Charge Retention via Segmentation
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Solution Overview
Problem
The continued scaling down of floating gate memory devices increases the sensitivity of charge retention characteristics to defects in the tunnel oxide, leading to potential charge leakage and data retention issues.
Innovation Solution
The use of nanodots instead of a monolithic floating gate distributes charge storage, reducing sensitivity to defects and incorporating an intergate dielectric layer and a spacing layer to encase and support the nanodots, preventing charge loss and data retention problems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the tunnel oxide thickness is reduced to enable further scaling down of memory devices, then the device can accommodate smaller feature sizes, but the charge retention characteristics become more sensitive to defects in the tunnel oxide
Solution Approach 1:
The patent segments the monolithic floating gate into multiple discrete nanodots distributed throughout the memory cell. This segmentation allows charge to be stored in multiple isolated locations rather than a single continuous structure. When defects occur in the tunnel oxide, only the nanodots adjacent to those defects are affected, while other nanodots continue to retain charge properly, thus resolving the sensitivity issue caused by thin tunnel oxide
2Device complexity
If a monolithic floating gate is used for charge storage, then the device structure is simpler, but the device becomes more sensitive to defects in the tunnel oxide
Solution Approach 1:
The monolithic floating gate is divided into multiple discrete nanodot structures. Each nanodot acts as an independent charge storage unit. This segmentation increases structural complexity but dramatically improves reliability by isolating the impact of tunnel oxide defects to only those nanodots immediately adjacent to the defects
Solution Approach 2:
The patent implements local quality by creating regions with different nanodot densities and configurations. Areas with higher defect density can have adjusted nanodot distributions to compensate, allowing different parts of the device to have optimized characteristics for their local conditions
3Use of energy by stationary object
If nanodots are distributed throughout the flash memory device, then the voltage required for storing information decreases and power consumption is reduced, but the device structure becomes more complex
Solution Approach 1:
The distributed nanodot structure segments the charge storage function across multiple small units rather than requiring a large monolithic gate. This enables lower operating voltages because each nanodot requires less voltage to charge, and the segmented structure can be addressed more efficiently, reducing overall power consumption despite increased structural complexity
Solution Approach 2:
The patent changes the fundamental parameter of charge storage from a continuous monolithic gate to discrete distributed nanodots. This parameter change enables lower voltage operation because the electric field required to charge individual nanodots is smaller than that needed for a large floating gate, thereby reducing power consumption
Data Source
AI summary
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.